EB675001DIP User Guide
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EB675001DIP User Guide

Simtec Electronics

B J Dooks

V R Sanders

Copyright © 2005 Simtec Electronics

  • ARM® is a registered trademark of ARM Limited.

  • LINUX® is a registered trademark of Linus Torvalds.

  • UNIX® is a registerd trademark of The Open Group.

  • All other trademarks are acknowledged.

The product described in this document is under continuous development and improvement. All descriptions of usage and particulars of the product are given in good faith by Simtec Electronics. However all warranties expressed or implied, including but not limited to implied warranties or merchantability, or fitness for purpose, are excluded.

While every precaution has been taken in the preparation of this book, the publisher assumes no responsibility for errors or omissions, or for damages resulting from the use of the information contained herein.

Revision History
Revision 1.0020th July 2005VRS

Initial Release.

Revision 1.0127th July 2005VRS

Formatting updates and improvements.

Revision 1.19th January 2006VRS

Improve design guide section.

Revision 1.114th April 2006VRS

Formatting updates and improvements.

Revision 1.212th April 2007VRS

Fix user CPLD pin numbering in Table 2.1, “60 way PTH connector PL3”.

Revision 1.35th October 2007VRS

Clarify IRQ0 use on the Section 2.6, “DM9000 Network controller” and Section 2.5, “Real Time Clock”.

Table of Contents

EB675001DIP Development Board
1. Overview
1.1. Kit contents
1.1.1. CD-ROM
1.1.2. EB675001DIP Development board
1.2. Development Tools
1.3. Using the development board
1.4. Handling precautions
2. Hardware Description
2.1. Overview
2.2. OKI ML675001 MCU
2.3. Memory
2.3.1. NOR boot flash
2.3.2. SRAM
2.3.3. SDRAM
2.3.4. EEPROM
2.4. JTAG
2.5. Real Time Clock
2.6. DM9000 Network controller
2.7. Xilinx CPLD
2.8. Serial port
2.9. Power Supply
2.10. Expansion connectors
3. Bootloader
3.1. Overview
3.2. Getting Started
3.2.1. Using hyperterm as a serial console
3.2.2. Using minicom as a serial console
4. Design Guide
4.1. Overview
4.2. Connections
4.3. Power Supply
4.4. User CPLD
A. Board Layout
B. Mechanical drawing

List of Figures

2.1. Detailed block diagram of the EB675001DIP
2.2. NOR flash to ML675001 attachment
2.3. SRAM to ML675001 attachment
2.4. SDRAM to ML675001 attachment
2.5. JTAG connector
2.6. DM9000 to ML675001 attachment
2.7. Xilinx XL9572XL to ML675001 attachment
2.8. Serial connector
2.9. Graph of EB675001DIP power usage
2.10. Expansion connector placement
3.1. Hyperterm settings window
3.2. Hyperterm displaying ABLE output
3.3. Minicom settings window
4.1. Schematic fragment using EB675001DIP Ethernet header
4.2. EB675001DIP header to multi-ICE JTAG cable schematic
4.3. EB675001DIP header to multi-ICE JTAG cable
4.4. Schematic fragment using on board EB675001DIP power regulation
4.5. Schematic fragment of flexible EB675001DIP power supply
4.6. Schematic fragment of DC-DC converter EB675001DIP power supply
4.7. Pseudo schematic fragment of EB675001DIP user CPLD
4.8. Webpack XWAIT schematic fragment
A.1. EB675001DIP board layout top side
A.2. EB675001DIP board layout bottom side
B.1. EB675001DIP Mechanical Drawing

List of Tables

2.1. 60 way PTH connector PL3
2.2. 60 way PTH connector PL4

List of Examples

3.1. Video display after starting ABLE on EB2410ITX
3.2. Serial display after starting ABLE on EB2410ITX
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