2.3. Memory

2.3.1. NOR boot flash
2.3.2. SRAM
2.3.3. SDRAM
2.3.4. EEPROM

2.3.1. NOR boot flash

The EB675001DIP has provision for a single NOR flash device. This device typically contains the bootloader and uCLinux image to boot, though it can contain anything the user requires. The flash is implemented as a single sixteen bit wide device, which is selected by use of the nROMCS chip select from the ML675001. This memory appears in bank 25 of the ML675001 memory map.

Figure 2.2. NOR flash to ML675001 attachment

NOR flash to ML675001 attachment

2.3.2. SRAM

The EB675001DIP has provision for an SRAM device, this is in addition to the 32KB of internal zero wait state memory that is internal to the ML675001. This memory is typically only fitted in the silver configuration of the board. The SRAM is implemented as a single sixteen bit wide device, which is selected by use of the nRAMCS chip select from the ML675001. This memory appears in bank 26 of the ML675001 memory map.

Figure 2.3. SRAM to ML675001 attachment

SRAM to ML675001 attachment

2.3.3. SDRAM

The EB675001DIP has provision for a single SDRAM device with either the default 256MBit capacity or a 512MBit capacity. This memory, where fitted, is accessed using the ML675001 SDRAM controller and appears in bank 24 of its memory map.

Figure 2.4. SDRAM to ML675001 attachment

SDRAM to ML675001 attachment

2.3.4. EEPROM

There is provision for a single EEPROM connected via the I2C bus. All specification boards have an 8KBit (1KB) device fitted as standard but up to 256KBit can be accommodated. The device is typically used to hold the non volatile settings in the ABLE bootloader.