2.10. Expansion connectors

2.10. Expansion connectors
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The EB675001DIP has two rows of standard 0.1inch Plated Through Hole (PTH) connectors, sometimes referred to as a QDIP configuration.

Figure 2.10. Expansion connector placement

These connectors provide all the I/O signals to expand the use of the module. For full details the EB675001DIP Connector and link pinouts document should be consulted, this contains addition information and comments relevant to using this product.

Table 2.1. 60 way PTH connector PL3

Description	Name	Pin	Pin	Name	Description
3.3V output from onboard regulator or external 3.3V regulated smoothed supply	3.3V	C1	D1	GND	Signal Ground
Supply Ground	GND	C2	D2	EXT_BAT	Supply for the Real Time Clock
Xilinx XC9572XL I/O Pin 92	CPLD_PIN92	C3	D3	CPLD_PIN91	Xilinx XC9572XL I/O Pin 91
Xilinx XC9572XL I/O Pin 89	CPLD_PIN89	C4	D4	CPLD_PIN90	Xilinx XC9572XL I/O Pin 90
Xilinx XC9572XL I/O Pin 86	CPLD_PIN86	C5	D5	CPLD_PIN87	Xilinx XC9572XL I/O Pin 87
Xilinx XC9572XL I/O Pin 82	CPLD_PIN82	C6	D6	CPLD_PIN85	Xilinx XC9572XL I/O Pin 85
Xilinx XC9572XL I/O Pin 79	CPLD_PIN79	C7	D7	CPLD_PIN81	Xilinx XC9572XL I/O Pin 81
Xilinx XC9572XL I/O Pin 77	CPLD_PIN77	C8	D8	CPLD_PIN78	Xilinx XC9572XL I/O Pin 78
Xilinx XC9572XL I/O Pin 74	CPLD_PIN74	C9	D9	CPLD_PIN76	Xilinx XC9572XL I/O Pin 76
Xilinx XC9572XL I/O Pin 71	CPLD_PIN71	C10	D10	CPLD_PIN72	Xilinx XC9572XL I/O Pin 72
Xilinx XC9572XL I/O Pin 68	CPLD_PIN68	C11	D11	CPLD_PIN70	Xilinx XC9572XL I/O Pin 70
Xilinx XC9572XL I/O Pin 66	CPLD_PIN66	C12	D12	CPLD_PIN67	Xilinx XC9572XL I/O Pin 67
Xilinx XC9572XL I/O Pin 64	CPLD_PIN64	C13	D13	CPLD_PIN65	Xilinx XC9572XL I/O Pin 65
Xilinx XC9572XL I/O Pin 61	CPLD_PIN61	C14	D14	CPLD_PIN63	Xilinx XC9572XL I/O Pin 63
Buffered CPU address line	SA[23]	C15	D15	CPLD_PIN60	Xilinx XC9572XL I/O Pin 60
Buffered CPU address line	SA[22]	C16	D16	CPLD_PIN59	Xilinx XC9572XL I/O Pin 59
Buffered CPU address line	SA[21]	C17	D17	GND	Signal ground
Buffered CPU address line	SA[20]	C18	D18	CPLD_PIN58	Xilinx XC9572XL I/O Pin 58
Buffered CPU address line	SA[19]	C19	D19	CPLD_PIN56	Xilinx XC9572XL I/O Pin 56
Buffered CPU address line	SA[18]	C20	D20	CPLD_PIN55	Xilinx XC9572XL I/O Pin 55
Buffered CPU address line	SA[17]	C21	D21	SA[8]	Buffered CPU address line
Buffered CPU address line	SA[16]	C22	D22	SA[7]	Buffered CPU address line
Buffered CPU address line	SA[15]	C23	D23	SA[6]	Buffered CPU address line
Buffered CPU address line	SA[14]	C24	D24	SA[5]	Buffered CPU address line
Buffered CPU address line	SA[13]	C25	D25	SA[4]	Buffered CPU address line
Buffered CPU address line	SA[12]	C26	D26	SA[3]	Buffered CPU address line
Buffered CPU address line	SA[11]	C27	D27	SA[2]	Buffered CPU address line
Buffered CPU address line	SA[10]	C28	D28	SA[1]	Buffered CPU address line
Buffered CPU address line	SA[9]	C29	D29	CPLD_PIN54	Xilinx XC9572XL I/O Pin 54
Signal Ground	GND	C30	D30	GND	Signal Ground (Key pin)

Table 2.2. 60 way PTH connector PL4

Description	Name	Pin	Pin	Name	Description
4.5 - 15V DC power supply	VIN	A1	B1	GND	Power ground
Power ground	GND	A2	B2	3.3V	3.3V output from onboard regulator or external 3.3V regulated smoothed supply
Xilinx XC9572XL I/O Pin 94	CPLD_PIN94	A3	B3	CPLD_PIN93	Xilinx XC9572XL I/O Pin 93
Xilinx XC9572XL I/O Pin 96	CPLD_PIN96	A4	B4	CPLD_PIN95	Xilinx XC9572XL I/O Pin 95
Xilinx XC9572XL I/O Pin 1	CPLD_PIN01	A5	B5	CPLD_PIN97	Xilinx XC9572XL I/O Pin 97
Xilinx XC9572XL I/O Pin 4	CPLD_PIN04	A6	B6	CPLD_PIN03	Xilinx XC9572XL I/O Pin 3
Xilinx XC9572XL I/O Pin 8	CPLD_PIN08	A7	B7	CPLD_PIN06	Xilinx XC9572XL I/O Pin 6
Inverted module reset output	RST	A8	B8	PWM1	Second Pulse Width Modulator output or CPU GPIO PIOC[1]
Inverted CPU fast interrupt line	FIQ	A9	B9	PWM0	First Pulse Width Modulator output or CPU GPIO PIOC[0]
Fourth CPU interrupt line or CPU GPIO 8	IRQ3	A10	B10	TC1	Terminal count for DMA Chanel 1 or CPU GPIO PIOB[4]
Third CPU interrupt line or CPU GPIO PIOE[7]	IRQ2	A11	B11	TC0	Terminal count for DMA Chanel 0 or CPU GPIO PIOB[5]
Second CPU interrupt line or CPU GPIO 6	IRQ1	A12	B12	DACK1	DMA acknowledge/clear for channel 1 or CPU GPIO PIOB[3]
First CPU interrupt line or CPU GPIO 5	IRQ0	A13	B13	DREQ1	DMA request for channel 1 or CPU GPIO PIOB[2]
I2C Serial Clock or CPU GPIO PIOE[4]	SCL	A14	B14	DACK0	DMA acknowledge/clear for channel 0 or CPU GPIO PIOB[1]
I2C Serial Data or CPU GPIO PIOE[3]	SDA	A15	B15	DREQ0	DMA request for channel 0 or CPU GPIO PIOB[0]
Synchronous serial (SSIO) data output	SDO	A16	B16	SRXD	Simple serial port (SIO) data receive (not the UART port) or CPU GPIO PIOB[7]
Synchronous serial (SSIO) data input	SDI	A17	B17	STXD	Simple serial port (SIO) data transmit or CPU GPIO PIOB[6]
Synchronous serial (SSIO) clock	SCK	A18	B18	RI	Unbuffered UART RI signal or CPU GPIO PIOA[7]
Signal ground	GND	A19	B19	RTS	Unbuffered UART RTS signal or CPU GPIO PIOA[6]
Fourth analog input	ANALOG_3	A20	B20	DTR	Unbuffered UART DTR signal or CPU GPIO PIOA[5]
Third analog input	ANALOG_2	A21	B21	DCD	Unbuffered UART DCD signal or CPU GPIO PIOA[4]
Second analog input	ANALOG_1	A22	B22	DSR	Unbuffered UART DSR signal or CPU GPIO PIOA[3]
First analog input	ANALOG_0	A23	B23	CTS	Unbuffered UART CTS signal or CPU GPIO PIOA[2]
Analog inputs ground reference	ANALOG_GND	A24	B24	TX	Unbuffered UART TX signal or CPU GPIO PIOA[1]
Analog inputs supply reference	VDD_ANALOG	A25	B25	RX	Unbuffered UART RX signal or CPU GPIO PIOA[0]
Buffered RS232 level UART DCD signal	RS232_DCD	A26	B26	RS232_DSR	Buffered RS232 level UART DSR signal
Buffered RS232 level UART RX signal	RS232_RX	A27	B27	RS232_RTS	Buffered RS232 level UART RTS signal
Buffered RS232 level UART TX signal	RS232_TX	A28	B28	RS232_CTS	Buffered RS232 level UART CTS signal
Buffered RS232 level UART DTR signal	RS232_DTR	A29	B29	RS232_RI	Buffered RS232 level UART RI signal
Serial port ground	GND	A30	B30	SERIAL_EN	RS232 buffer enable

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