2.10. Expansion connectors

The EB675001DIP has two rows of standard 0.1inch Plated Through Hole (PTH) connectors, sometimes referred to as a QDIP configuration.

Figure 2.10. Expansion connector placement

Expansion connector placement

These connectors provide all the I/O signals to expand the use of the module. For full details the EB675001DIP Connector and link pinouts document should be consulted, this contains addition information and comments relevant to using this product.

Table 2.1. 60 way PTH connector PL3

3.3V output from onboard regulator or external 3.3V regulated smoothed supply3.3VC1D1GNDSignal Ground
Supply GroundGNDC2D2EXT_BATSupply for the Real Time Clock
Xilinx XC9572XL I/O Pin 92CPLD_PIN92C3D3CPLD_PIN91Xilinx XC9572XL I/O Pin 91
Xilinx XC9572XL I/O Pin 89CPLD_PIN89C4D4CPLD_PIN90Xilinx XC9572XL I/O Pin 90
Xilinx XC9572XL I/O Pin 86CPLD_PIN86C5D5CPLD_PIN87Xilinx XC9572XL I/O Pin 87
Xilinx XC9572XL I/O Pin 82CPLD_PIN82C6D6CPLD_PIN85Xilinx XC9572XL I/O Pin 85
Xilinx XC9572XL I/O Pin 79CPLD_PIN79C7D7CPLD_PIN81Xilinx XC9572XL I/O Pin 81
Xilinx XC9572XL I/O Pin 77CPLD_PIN77C8D8CPLD_PIN78Xilinx XC9572XL I/O Pin 78
Xilinx XC9572XL I/O Pin 74CPLD_PIN74C9D9CPLD_PIN76Xilinx XC9572XL I/O Pin 76
Xilinx XC9572XL I/O Pin 71CPLD_PIN71C10D10CPLD_PIN72Xilinx XC9572XL I/O Pin 72
Xilinx XC9572XL I/O Pin 68CPLD_PIN68C11D11CPLD_PIN70Xilinx XC9572XL I/O Pin 70
Xilinx XC9572XL I/O Pin 66CPLD_PIN66C12D12CPLD_PIN67Xilinx XC9572XL I/O Pin 67
Xilinx XC9572XL I/O Pin 64CPLD_PIN64C13D13CPLD_PIN65Xilinx XC9572XL I/O Pin 65
Xilinx XC9572XL I/O Pin 61CPLD_PIN61C14D14CPLD_PIN63Xilinx XC9572XL I/O Pin 63
Buffered CPU address lineSA[23]C15D15CPLD_PIN60Xilinx XC9572XL I/O Pin 60
Buffered CPU address lineSA[22]C16D16CPLD_PIN59Xilinx XC9572XL I/O Pin 59
Buffered CPU address lineSA[21]C17D17GNDSignal ground
Buffered CPU address lineSA[20]C18D18CPLD_PIN58Xilinx XC9572XL I/O Pin 58
Buffered CPU address lineSA[19]C19D19CPLD_PIN56Xilinx XC9572XL I/O Pin 56
Buffered CPU address lineSA[18]C20D20CPLD_PIN55Xilinx XC9572XL I/O Pin 55
Buffered CPU address lineSA[17]C21D21SA[8]Buffered CPU address line
Buffered CPU address lineSA[16]C22D22SA[7]Buffered CPU address line
Buffered CPU address lineSA[15]C23D23SA[6]Buffered CPU address line
Buffered CPU address lineSA[14]C24D24SA[5]Buffered CPU address line
Buffered CPU address lineSA[13]C25D25SA[4]Buffered CPU address line
Buffered CPU address lineSA[12]C26D26SA[3]Buffered CPU address line
Buffered CPU address lineSA[11]C27D27SA[2]Buffered CPU address line
Buffered CPU address lineSA[10]C28D28SA[1]Buffered CPU address line
Buffered CPU address lineSA[9]C29D29CPLD_PIN54Xilinx XC9572XL I/O Pin 54
Signal GroundGNDC30D30GNDSignal Ground (Key pin)

Table 2.2. 60 way PTH connector PL4

4.5 - 15V DC power supplyVINA1B1GNDPower ground
Power groundGNDA2B23.3V3.3V output from onboard regulator or external 3.3V regulated smoothed supply
Xilinx XC9572XL I/O Pin 94CPLD_PIN94A3B3CPLD_PIN93Xilinx XC9572XL I/O Pin 93
Xilinx XC9572XL I/O Pin 96CPLD_PIN96A4B4CPLD_PIN95Xilinx XC9572XL I/O Pin 95
Xilinx XC9572XL I/O Pin 1CPLD_PIN01A5B5CPLD_PIN97Xilinx XC9572XL I/O Pin 97
Xilinx XC9572XL I/O Pin 4CPLD_PIN04A6B6CPLD_PIN03Xilinx XC9572XL I/O Pin 3
Xilinx XC9572XL I/O Pin 8CPLD_PIN08A7B7CPLD_PIN06Xilinx XC9572XL I/O Pin 6
Inverted module reset outputRSTA8B8PWM1Second Pulse Width Modulator output or CPU GPIO PIOC[1]
Inverted CPU fast interrupt lineFIQA9B9PWM0First Pulse Width Modulator output or CPU GPIO PIOC[0]
Fourth CPU interrupt line or CPU GPIO 8IRQ3A10B10TC1Terminal count for DMA Chanel 1 or CPU GPIO PIOB[4]
Third CPU interrupt line or CPU GPIO PIOE[7]IRQ2A11B11TC0Terminal count for DMA Chanel 0 or CPU GPIO PIOB[5]
Second CPU interrupt line or CPU GPIO 6IRQ1A12B12DACK1DMA acknowledge/clear for channel 1 or CPU GPIO PIOB[3]
First CPU interrupt line or CPU GPIO 5IRQ0A13B13DREQ1DMA request for channel 1 or CPU GPIO PIOB[2]
I2C Serial Clock or CPU GPIO PIOE[4]SCLA14B14DACK0DMA acknowledge/clear for channel 0 or CPU GPIO PIOB[1]
I2C Serial Data or CPU GPIO PIOE[3]SDAA15B15DREQ0DMA request for channel 0 or CPU GPIO PIOB[0]
Synchronous serial (SSIO) data outputSDOA16B16SRXDSimple serial port (SIO) data receive (not the UART port) or CPU GPIO PIOB[7]
Synchronous serial (SSIO) data inputSDIA17B17STXDSimple serial port (SIO) data transmit or CPU GPIO PIOB[6]
Synchronous serial (SSIO) clockSCKA18B18RIUnbuffered UART RI signal or CPU GPIO PIOA[7]
Signal groundGNDA19B19RTSUnbuffered UART RTS signal or CPU GPIO PIOA[6]
Fourth analog inputANALOG_3A20B20DTRUnbuffered UART DTR signal or CPU GPIO PIOA[5]
Third analog inputANALOG_2A21B21DCDUnbuffered UART DCD signal or CPU GPIO PIOA[4]
Second analog inputANALOG_1A22B22DSRUnbuffered UART DSR signal or CPU GPIO PIOA[3]
First analog inputANALOG_0A23B23CTSUnbuffered UART CTS signal or CPU GPIO PIOA[2]
Analog inputs ground referenceANALOG_GNDA24B24TXUnbuffered UART TX signal or CPU GPIO PIOA[1]
Analog inputs supply referenceVDD_ANALOGA25B25RXUnbuffered UART RX signal or CPU GPIO PIOA[0]
Buffered RS232 level UART DCD signalRS232_DCDA26B26RS232_DSRBuffered RS232 level UART DSR signal
Buffered RS232 level UART RX signalRS232_RXA27B27RS232_RTSBuffered RS232 level UART RTS signal
Buffered RS232 level UART TX signalRS232_TXA28B28RS232_CTSBuffered RS232 level UART CTS signal
Buffered RS232 level UART DTR signalRS232_DTRA29B29RS232_RIBuffered RS232 level UART RI signal
Serial port groundGNDA30B30SERIAL_ENRS232 buffer enable