Simtec Electronics Power management Unit Registers |
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Contents
©2007, 2008 Simtec Electronics
Introduction
The Simtec Power Management Unit (IPSTCPMU) is accessed by an I2C bus. The unit is single byte addressed at 0x6b. The unit controls the power and miscellaneous GPIO.
The PMU has the ability to generate an internal IRQ (Note: this is NOT a CPU IRQ) which may be configured by unmasking GPIO marked as input. The IRQ will not have any effect (beyond being readable in the IRQ status register) unless the global IRQ enable is set.
If an unmasked PMU IRQ is generated the unit will assert its CPU IRQ line to alert the main processor (which may be used by the CPU as a wakeup source). In addition the PMU will turn the power on if the system is not already on.
V1.1 Registers
The first version of the PMU was never released and will never be found in products.
V1.2 Registers
| Register | |||||
|---|---|---|---|---|---|
| Number | Width | Read Value | Write Value | EEP | |
| Dec | Hex | ||||
| 0 | 0 | 4 | Ident "SBPM" | - | |
| 1 | 1 | 1 | PMU Version (2) | - | |
| 2 | 2 | 1 | DDC Enable state | Non zero to enable DDC | |
| 3 | 3 | 1 | - | Guard byte to Power off | |
| 4 | 4 | 1 | - | Guard byte to reset system | |
| 5 | 5 | 1 | Global Wake on status | Non zero to enable Wake | Y |
| 6 | 6 | 1 | Wake on LAN enabled | Non zero to enable WOL | Y |
| 7 | 7 | 1 | Wake on Ring enabled | Non zero to enable WOR | Y |
| 8 | 8 | 1 | - | System beep value is freq | |
| 9 | 9 | 6 | PMU Unique ID bytes | Unique ID bytes (Write once) | Y |
| 10 | A | 1 | - | Guard byte to sleep | |
| 192 - 255 | C0 - FF | 1 | EEPROM memory | EEPROM memory | |
The guard byte value is 85 (0x55).
Registers marked EEP are stored and set on powerup.
Unique ID is writable once if its never been set before.
Global wakeup is non zero to enable wakeup sources.
Wakeup is defined as enabling power (if not already on) and signalling the CPU with an IRQ.
EEPROM memory on the V1 devices included the write once memory for the uid and all the settings memory as there were 64 bytes total, on the V2 devices its 64bytes of unterrupted user space.
V1.3 Registers
Version 1.3 is backwards compatible, the protocol version register has been updated to 30 (0x1E) to indicate the additional capabilities.
A minor protocol version increase to 31 (0x1F) was perfomed to add the both edge polarity registers.
A minor protocol version increase to 32 (0x20) was performed to add the ability to change the both-edge polarity register. Also the version register gained an extra byte to indicate board specific version information.
The version 1.33 PMU system has a more sophisticated IRQ handling system. An internal IRQ will interrupt the main processor assuming the global IRQ enable (register 5) is set. This also allows for flexible board wake up, as all the processor requires in order to wake the system up is an IRQ. The general purpose nature of this system means that, in addition to the wakeup function, interrupts can be generated whilst running (if configured for it) perhaps to indicate voltage margin conditions etc.
| Register | |||||
|---|---|---|---|---|---|
| Number | Width | Read Value | Write Value | EEP | |
| Dec | Hex | ||||
| 01 | 0 | 4 | Ident "SBPM" | - | |
| 1 | 1 | 2 | PMU Version | - | |
| 21 | 2 | 1 | DDC Enable state | Non zero to enable DDC | |
| 31 | 3 | 1 | - | Guard byte to Power off 3 | |
| 41 | 4 | 1 | - | Guard byte to reset system 3 | |
| 5 | 5 | 1 | Global IRQ enable status | Non zero to enable IRQs | Y |
| 61 | 6 | 1 | Wake on LAN enabled | Non zero to enable WOL | Y |
| 71 | 7 | 1 | Wake on Ring enabled | Non zero to enable WOR | Y |
| 81 | 8 | 1 | - | System beep value is freq | |
| 91 | 9 | 6 | PMU Unique ID bytes | Unique ID bytes (Write once) | Y |
| 101 | A | 1 | - | Guard byte to sleep 3 | |
| 11 | B | 1 | PMU Status of last op. | - | |
| 125 | C | 5 | Hardware specific information. | - | |
| 136 | D | 4 | Implementation specific. | Implementation specific. | |
| 20 | 14 | n | GPIO present bits | - | |
| 21 | 15 | n | GPIO Pullup settings | GPIO Pullup settings | Y |
| 22 | 16 | n | Data Direction bitmask | DDR - 1 for out 0 for in | Y |
| 23 | 17 | n | Current GPIO status | Bits to set on | |
| 24 | 18 | n | Current GPIO status | Bits to clear off | |
| 25 | 19 | n | GPIO IRQ source mask | GPIO IRQ source mask | Y |
| 26 | 1A | n | GPIO IRQ edge/level | GPIO IRQ edge or level | Y |
| 27 | 1B | n | GPIO IRQ polarity | GPIO IRQ source polarity | Y |
| 28 | 1C | n | GPIO IRQ status | Clear pending IRQ | |
| 29 | 1D | n | GPIO delay mask | GPIO delay mask | Y |
| 30 | 1E | 1 | GPIO delay value (dS) | GPIO delay value | Y |
| 312 | 1F | n | GPIO edge IRQ both edges | GPIO IRQ both edges | Y |
| 322 | 20 | n | GPIO first IRQ status | Clear status | |
| 332 | 21 | n | GPIO unmasked IRQ status | - | |
| 395 | 27 | 4 | ADC Max deflection and VREF value | - | |
| 40 | 28 | 1 | ADC present | - | |
| 41 | 29 | 1 | ADC IRQ source mask | ADC IRQ source mask | Y |
| 42 | 2A | 1 | ADC IRQ status | Clear pending IRQ | |
| 43 | 2B | 1 | ADC compare polarity | ADC compare polarity | Y |
| 44 | 2C | 2 | ADC 0 value | - | |
| 45 | 2D | 2 | ADC 1 value | - | |
| 46 | 2E | 2 | ADC 2 value | - | |
| 47 | 2F | 2 | ADC 3 value | - | |
| 48 | 30 | 2 | ADC 4 value | - | |
| 49 | 31 | 2 | ADC 5 value | - | |
| 50 | 32 | 2 | ADC 6 value | - | |
| 51 | 33 | 2 | ADC 7 value | - | |
| 525 | 34 | 2 | ADC 0 Threshold value | ADC 0 Threshold value | Y |
| 535 | 35 | 2 | ADC 1 Threshold value | ADC 1 Threshold value | Y |
| 545 | 36 | 2 | ADC 2 Threshold value | ADC 2 Threshold value | Y |
| 555 | 37 | 2 | ADC 3 Threshold value | ADC 3 Threshold value | Y |
| 565 | 38 | 2 | ADC 4 Threshold value | ADC 4 Threshold value | Y |
| 575 | 39 | 2 | ADC 5 Threshold value | ADC 5 Threshold value | Y |
| 585 | 3A | 2 | ADC 6 Threshold value | ADC 6 Threshold value | Y |
| 595 | 3B | 2 | ADC 7 Threshold value | ADC 7 Threshold value | Y |
| 647 | 40 | 2 | WDG: Power-on/Reset. Current and reset values in seconds. | WDG: Power-on/Reset. Current value and optionally reset value in seconds. | Y |
| 657 | 41 | 1 | Bus heartbeat reset value in seconds. 0 is disabled. | Bus heartbeat reset value in seconds. 0 to disable heartbeat, nonzero to enable it at a given periodicity. | N |
| 668 | 42 | 1 | Maximum watchdog recoveries before the PMU locks down. 0 is disabled. | Maximum number of times the watchdog is permitted to recover the system before it locks out the IRQs and powers down the board. Write a 0 to disable this feature. | N |
| 128 | 1 | 6 | Scratchpad (DEBUG) | Scratchpad (DEBUG) | |
Note 1: These registers are the same as those in protocol version 1.2
Note 2: These registers were introduced in protocol version 1.31.
Note 3: The guard byte value is 85 (0x55)
Note 4: This register was made read/write in protocol version 1.32 and was read-only prior to that.
Note 5: These registers were made available in protocol version 1.32.
Note 6: This register was made available in protocol version 1.33.
Note 7: This register was made available in protocol version 1.34.
Note 8: This register was made available in protocol version 1.35.
General registers
The version register first byte gives the protocol version, the second byte is the implementation version of the PMU.
The hardware specific information register returns data about the PMU hardware itself. The first byte indicates what kind of hardware is implementing the PMU and the rest of the response is hardware specific. This register is reserved for Simtec debug.
GPIO registers
- The "GPIO present" bits indicate which GPIOs are present and being used. The first fully zero byte read indicates the end of the register.
- Pullups may be enabled individually. Set the corresponding bit to enable the pullup.
- Data direction may be set individually. Set the corresponding bit for output, clear it for input.
- To set a bit, write a 1 at the relevant index to the 'set' register.
- To clear a bit, write a 1 at the relevant index to the 'clear' register.
- An IRQ may be generated from any GPIO source by setting the relevant bit in the IRQ source mask.
- The IRQ type may be set individually. Set the bit for level interrupts, clear it for edge interrupts.
- The IRQ polarity selects if high (set) or low (clear) is the active status for level interrupt sources or the rising edge (set) and falling edge (clear) for edge triggered interrupts.
- The IRQ source polarity is Exclusive-ORed (XOR) with the current status and then ANDed with the IRQ mask.
- When an IRQ occurs the relevant bit is set in the IRQ status register. The IRQ is cleared by writing a 1 to the relevant index in the status register. In addition if the "GPIO first IRQ status" register is clear the bit will also be set in this register. Further incoming IRQs will not alter the "GPIO first IRQ status" register until it is cleared by writing any value to it.
- By not explicitly fixing the register width this allows an implementation of the protocol to add as many GPIO bits as required. This removes the need for additional GPIO registers in the future which would require a protocol change.
- Only as many bytes as required need be written or read. I.E. if only the bottom 8 bits are interesting, single byte read/writes will suffice the rest of the register will be unchanged.
- Some bits may be "sticky" if an implementation does not allow for them to change e.g. locked pullups or input only pins.
- Unused bits will read 0. Which would mean "no pullup" or "pin is input" as appropriate. Such clear bits cannot be used in the IRQ source or polarity registers.
ADC registers
- The information register provides the maximum deflection and voltage reference in millivolts as two MSB words in a four byte response.
- Those ADCs present, provide the raw ADC values as two bytes, left aligned.
- The 16 bit registers read in most significant byte first order.
- Reading only one byte is possible if 8 bits of accuracy is sufficient.
- IRQ sources can be enabled for the ADCs, allowing the inputs to be compared against a specified value.
- ADC comparators allow you to specify whether to interrupt when the input rises above, or falls below the specified threshold value.
- A bit set in the polarity register indicates that the IRQ is triggered by rising above the threshold value, a clear bit indicates that the IRQ is triggered by falling below the threshold value.
- IRQ status register behaves the same as the GPIO registers.
- Unused ADC channels read as 0 and IRQs cannot be requested for those ADCs.
- Analog inputs therefore act as wake IRQs. However, such functionality has power usage implications.
Watchdog (WDG) registers
- Each value is 1 byte, in seconds.
- Each register carries one or two values, the first is the current value of the watchdog timer, the second is the reset value of the timer if it is EEPROM backed.
- Writing the current value starts the watchdog.
- Only the reset value is EEPROM backed.
- If the current value is zero, the watchdog is disabled.
- If only a single value is in the register, it is the reset value and it is not EEPROM backed.
Bus heartbeat register
- The heartbeat is expressed in seconds.
- Whenever the heartbeat timer expires, the PO/R watchdog is activated if it is idle, and the CPU IRQ is raised.
- The bus heartbeat watchdog will be stopped whenever the board is powered off or reset using the PMU. It defaults to disabled and will disarm itself should the PO/R watchdog fire.
Suggested watchdog usage
It is recommended that the following sequence be used when the watchdogs are desired.
- The PO/R reset value is set to something sensible such as 2 minutes.
- ABLE's startup will cause the PO/R to stop as it will address the PMU.
- Just before you start Linux, enable the bus heartbeat at something like ten seconds.
- This means that in 2 minutes and 10 seconds the board will reset. Assuming your Linux installation gets the PMU driver up by then (trivial if it is built into the kernel) this won't be an issue.
- Every 10 seconds, the bus heartbeat will raise an IRQ to the processor. The driver will probe the PMU to ask what happened, which will stop the PO/R watchdog.
- If you suspend the board, it would be sensible to disable the bus heartbeat before suspend, otherwise the heartbeat will wake the processor up again.