IM2440D20 Connector pinouts |
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Contents
- Introduction
- Edge connector physical layout
- Edge connector pin number layout
- Edge connector pins by function
©2006 Simtec Electronics
$Id: pinlist.html 14541 2007-09-25 22:44:06Z vince $
Introduction
This document shows the pinouts for the IM2440D20. There are also notes and warnings on using the module in an application.
Several pins presented here have alternate functions on the S3c2440 CPU, they may obviously be used for their alternate function. A pins primay use is detailed here, other modules in the D200 range using other processors may not have the alternate functions.
IM2440D20 edge connector physical layout
IM2440D20 edge connector pinouts by pin number
Pin | Signal | Description |
---|---|---|
1 | VOUT | Output supply from module |
2 | GND | Ground |
3 | nFRE | Inverted read enable |
4 | ALE | NAND address latch enable |
5 | nFWE | NAND Inverted write enable |
6 | CLE | NAND Command latch enable |
7 | nFCE<2> | Third NAND chip select |
8 | R/nB | NAND ready/not busy |
9 | D<0> | Data bus bit 0 |
10 | D<16> | Data bus bit 16 |
11 | D<1> | Data bus bit 1 |
12 | D<17> | Data bus bit 17 |
13 | D<2> | Data bus bit 2 |
14 | D<18> | Data bus bit 18 |
15 | D<3> | Data bus bit 3 |
16 | D<19> | Data bus bit 19 |
17 | D<4> | Data bus bit 4 |
18 | D<20> | Data bus bit 20 |
19 | D<5> | Data bus bit 5 |
20 | D<21> | Data bus bit 21 |
21 | D<6> | Data bus bit 6 |
22 | D<22> | Data bus bit 22 |
23 | D<7> | Data bus bit 7 |
24 | D<23> | Data bus bit 23 |
25 | D<8> | Data bus bit 8 |
26 | D<24> | Data bus bit 24 |
27 | D<9> | Data bus bit 9 |
28 | D<25> | Data bus bit 25 |
29 | D<10> | Data bus bit 10 |
30 | D<26> | Data bus bit 26 |
31 | D<11> | Data bus bit 11 |
32 | D<27> | Data bus bit 27 |
33 | D<12> | Data bus bit 12 |
34 | D<28> | Data bus bit 28 |
35 | D<13> | Data bus bit 13 |
36 | D<29> | Data bus bit 29 |
37 | D<14> | Data bus bit 14 |
38 | D<30> | Data bus bit 30 |
39 | D<15> | Data bus bit 15 |
40 | D<31> | Data bus bit 31 |
41 | GND | Ground |
42 | GND | Ground |
43 | nWBE<0> | First inverted write byte enable |
44 | BUF_EN | Buffer enable |
45 | nWBE<1> | Second inverted write byte enable |
46 | BUF_DIR | Buffer direction |
47 | nWBE<2> | Third inverted write byte enable |
48 | PWN_EN | Power good output |
49 | nWBE<3> | Forth inverted write byte enable |
50 | nRESET | Inverted reset output |
51 | nWAIT | Inverted I/O wait signal |
52 | nCS<1> | First inverted chip select |
53 | nIOCS16 | Inverted sixteen bit access select |
54 | nCS<2> | Second inverted chip select |
55 | nRD | Inverted read select |
56 | nCS<3> | Third inverted chip select |
57 | nWR | Inverted write select |
58 | nCS<4> | Fourth inverted chip select |
59 | GND | Ground |
60 | nCS<5> | Fifth inverted chip select |
61 | A<0> | Address bus bit 0 |
62 | A<15> | Address bus bit 15 |
63 | A<1> | Address bus bit 1 |
64 | A<16> | Address bus bit 16 |
65 | A<2> | Address bus bit 2 |
66 | A<17> | Address bus bit 17 |
67 | A<3> | Address bus bit 3 |
68 | A<18> | Address bus bit 18 |
69 | A<4> | Address bus bit 4 |
70 | A<19> | Address bus bit 19 |
71 | A<5> | Address bus bit 5 |
72 | A<20> | Address bus bit 20 |
73 | A<6> | Address bus bit 6 |
74 | A<21> | Address bus bit 21 |
75 | A<7> | Address bus bit 7 |
76 | A<22> | Address bus bit 22 |
77 | A<8> | Address bus bit 8 |
78 | A<23> | Address bus bit 23 |
79 | A<9> | Address bus bit 9 |
80 | A<24> | Address bus bit 24 |
81 | A<10> | Address bus bit 10 |
82 | A<25> | Address bus bit 25 |
83 | A<11> | Address bus bit 11 |
84 | A<26> | Address bus bit 26 |
85 | A<12> | Address bus bit 12 |
86 | TCLK0 | Timer 0 output |
87 | A<13> | Address bus bit 13 |
88 | TOUT<0> | First PWM output |
89 | A<14> | Address bus bit 14 |
90 | TOUT<1> | Second PWM output |
91 | GND | Ground |
92 | TOUT<2> | Third PWM output |
93 | DACK<0> | First DMA acknowledge |
94 | TOUT<3> | Fourth PWM output |
95 | DREQ<0> | First DMA request |
96 | DACK<1> | Second DMA acknowledge |
97 | I2S_LRCK | I2S left right select |
98 | DREQ<1> | Second DMA request |
99 | I2S_CLK | I2S clock |
100 | EINT<0> | External interrupt 0 |
101 | I2S_CDCLK | I2S command/data select |
102 | EINT<1> | External interrupt 1 |
103 | I2S_SDI | I2S serial data in |
104 | EINT<2> | External interrupt 2 |
105 | I2S_SDO | I2S serial data out |
106 | EINT<3> | External interrupt 3 |
107 | SDCLK | SD card clock |
108 | EINT<4> | External interrupt 4 |
109 | SDCMD | SD card command |
110 | EINT<5> | External interrupt 5 |
111 | SDDATA<0> | SD card first data line |
112 | EINT<6> | External interrupt 6 |
113 | SDDATA<1> | SD card second data line |
114 | EINT<7> | External interrupt 7 |
115 | SDDATA<2> | SD card third data line |
116 | EINT<8> | External interrupt 8 |
117 | SDDATA<3> | SD card fourth data line |
118 | EINT<9> | External interrupt 9 |
119 | SPIMISO | SPI bus master in slave out |
120 | EINT<10> | External interrupt 10 |
121 | SPIMOSI | SPI bus master out slave in |
122 | EINT<11> | External interrupt 11 |
123 | SPICLK | SPI bus clock |
124 | EINT<12> | External interrupt 12 |
125 | SCL | I2C bus clock |
126 | EINT<13> | External interrupt 13 |
127 | SDA | I2C bus data |
128 | EINT<14> | External interrupt 14 |
129 | GND | Ground |
130 | EINT<15> | External interrupt 15 |
131 | LEND | Line end |
132 | EINT<16> | External interrupt 16 |
133 | VCLK | Video clock |
134 | RTS<1> | Second serial port request to send |
135 | HS | Horizontal sync |
136 | CTS<1> | Second serial port clear to send |
137 | VS | Vertical sync |
138 | EINT<19> | External interrupt 19 |
139 | DE/VM | Video data enable |
140 | CTS<0> | First serial port Clear To Send |
141 | VD<0> | Video bus bit 0 |
142 | RTS<0> | First serial port Request To Send |
143 | VD<1> | Video bus bit 1 |
144 | TX<0> | First serial port transmit |
145 | VD<2> | Video bus bit 2 |
146 | RX<0> | First serial port recive |
147 | VD<3> | Video bus bit 3 |
148 | TX<1> | Second serial port transmit |
149 | VD<4> | Video bus bit 4 |
150 | RX<1> | Second serial port recive |
151 | VD<5> | Video bus bit 5 |
152 | TX<2> | Third serial port transmit |
153 | VD<6> | Video bus bit 6 |
154 | RX<1> | Third serial port recive |
155 | VD<7> | Video bus bit 7 |
156 | VOUT | Output supply from module |
157 | VD<8> | Video bus bit 8 |
158 | GND | Analog Ground |
159 | VD<9> | Video bus bit 9 |
160 | ADC<0> | Analog input 0 |
161 | VD<10> | Video bus bit 10 |
162 | ADC<1> | Analog input 1 |
163 | VD<11> | Video bus bit 11 |
164 | ADC<2> | Analog input 2 |
165 | VD<12> | Video bus bit 12 |
166 | ADC<3> | Analog input 3 |
167 | VD<13> | Video bus bit 13 |
168 | ADC<4> | Analog input 4 |
169 | VD<14> | Video bus bit 14 |
170 | ADC<5> | Analog input 5 |
171 | VD<15> | Video bus bit 15 |
172 | ADC<6> | Analog input 6 |
173 | VD<16> | Video bus bit 16 |
174 | ADC<7> | Analog input 7 |
175 | VD<17> | Video bus bit 17 |
176 | GND | Ground |
177 | VD<18> | Video bus bit 18 |
178 | DN<0> | Data negative for USB port 0 |
179 | VD<19> | Video bus bit 19 |
180 | DP<0> | Data positive for USB port 0 |
181 | VD<20> | Video bus bit 20 |
182 | DN<1> | Data negative for USB port 0 |
183 | VD<21> | Video bus bit 21 |
184 | DP<1> | Data positive for USB port 1 |
185 | VD<22> | Video bus bit 22 |
186 | nTRST | Inverted tap reset |
187 | VD<23> | Video bus bit 23 |
188 | TDI | Tap data input |
189 | GND | Ground |
190 | TMS | Tap mode select |
191 | VCC_RTC | Real time clock supply |
192 | TCK | Tap clock |
193 | VIN | Power supply |
194 | TDO | Tap data out |
195 | VIN | Power supply |
196 | nRESET | Inverted reset input |
197 | VIN | Power supply |
198 | GND | Ground |
199 | VIN | Power supply |
200 | GND | Ground |
IM2440D20 edge connector pins by function
Power supply
Function | Pins |
---|---|
VIN | 193, 195, 197, 199 |
VOUT | 1, 156 |
GND | 2, 41, 42, 59, 91, 129, 158, 176, 189, 198, 200 |
The module is powered from four input pins (VIN) from which it generates all necessary internal voltages. This is achieved with a Texas Instruments TPS65011, this device is controlled from the CPU by using the I2C bus and is at address 0x24.
The nominal input operating voltages are 3.3 to 5V with a 5% tolerance. The absolute maximum ratings are 3.15V to 5.5V. The modules typical power consumption is 0.5W (150mA at 3.3V) when operating in a normal configuration at 400MHz.
The two output pins (VOUT) provide output supply from the modules internal main power bus. The main bus is configured to default to 3.0V operation (this still lies within the typical 10% margin allowed for supplies on 3.3V devices) which saves power and gives a wider input operating voltage.
The VOUT output may be used to supply up to 300mA at 3.3V absolute maximum. The output must not be connected to the input supply or damage will occur. The output voltage will never exceed the input supply despite the output voltage selection.
The modules main supply voltage may be altered to one of 3.3, 3.0, 2.75 or 2.5V once the system is running, however correct module operations for settings below 3.0V are not guaranteed.
Extenal peripheral bus
Function | Pins |
---|---|
nWBE<0 - 3> | 43,45,47,49 |
nCS<1 - 5> | 52,54,56,58,60 |
nWAIT | 51 |
nIOCS16 | 53 |
nRD | 55 |
nWR | 57 |
BUF_EN | 44 |
BUF_DIR | 46 |
A<0 - 26> | 61 - 84 |
D<0 - 31> | 9 - 40 |
Video
Function | Pins |
---|---|
LEND | 131 |
VCLK | 133 |
HS | 135 |
VS | 137 |
DE/VM | 139 |
VD<0 - 23> | 141, 143, 145, 147, 149, 151, 153, 155, 157, 159, 161, 163, 165, 167, 169, 171, 173, 175, 177, 179, 181, 183, 185, 187 |
The digital video bus allows for up to 24bit video output direct from the S3C2440. The bus may be reconfigured as required for the specific video requirements.