The S3C2410 and the system CPLD are connected to a single JTAG chain. The JTAG chain is available from this 0.1inch 20way connector and allows reprogramming of the user CPLD and ICE debugging of the processor. This connector has the standard ARM Multi-ICE pinout so most JTAG debuggers will be compatible.
Table 2.1. JTAG connector PL18
| Pin | Name | Description |
|---|---|---|
| 1 | 3.3V | 3.3V supply |
| 2 | 3.3V | 3.3V supply |
| 3 | nTRST | Inverted Tap reset |
| 4 | GND | Signal Ground |
| 5 | TDI | Data In |
| 6 | GND | Signal Ground |
| 7 | TMS | |
| 8 | GND | Signal Ground |
| 9 | TCK | |
| 10 | GND | Signal Ground |
| 11 | RCLK | Return clock, pulled down with 390ohm to ground |
| 12 | GND | Signal Ground |
| 13 | TDO | Tap data out |
| 14 | GND | Signal Ground |
| 15 | nSRST | Inverted system reset |
| 16 | GND | Signal Ground |
| 17 | N/C | Not connected |
| 18 | GND | Signal Ground |
| 19 | N/C | Not connected |
| 20 | GND | Signal Ground |
The JTAG chain on the EB2410ITX is connected to the S3C2410 and system CPLD. Because of this care should be taken to ensure the system CPLD is placed in bypass. BSDL files are available from Samsung for the S3C2410 and Xilinx for the CPLD device.