Simtec Electronics

EB2410ITX Physical Memory Map

AuthorVRS, BJD, GS


©2007 Simtec Electronics


This document shows the physical memory layout of the EB2410ITX which is available in addition to that specified in the Samsung 2410 datasheet.

All memory locations given in this document are physical addresses as seen by the Samsung S3C2410 SOC. Access to these memory addresses may be translated by the processors Memory Management Unit (MMU) configured by the bootloader or Operating System (OS) being executed.

All addresses are shown in Hexadecimal unless otherwise specified.

The physical memory map decoded by the S3C2410 external memory controller, that is memory mapped I/O which affects external pins, is the first gigabyte of address space.

The S3C2410 SOC has numerous other peripherals which are mapped outside of this first gigabyte and are covered in the S3C2410 I/O Special Function Registers section.

The EB2410ITX (bast) board includes the following IO devices for peripheral connectivity.

The Asix Ethernet adaptor and Super I/O controller are optional and may not be fitted to some versions of the EB2410ITX.


Region Start Address End Address Device
ROM 00000000 01FFFFFF ROM
ROM, LCD, CPLD 08000000 09FFFFFF LCD Module 1
0A000000 0BFFFFFF LCD Module 2
0C000000 0DFFFFFF Alternate ROM mapping
0E000000 0FFFFFFF Board Control Registers
External I/O 10000000 17FFFFFF 8bit access - slow cycle
18000000 1FFFFFFF 16bit access - slow cycle
20000000 27FFFFFF 16bit access - medium cycle
28000000 2FFFFFFF 16bit access - fast cycle
S3C2410 I/O 48000000 5FFFFFFF S3C2410 Internal peripherals (SFR)
Memory 30000000 37FFFFFF SDram bank 0
38000000 3FFFFFFF SDram bank 1


ROM region

The EB2410ITX has a single NOR flash site used as a ROM. The device may be up to 256 mega bits (32 mega bytes) in size but typically a 16 megabit (2 megabyte) device is fitted. In this region this device is read only and writes are inhibited.

Alternate ROM, LCD, Board Control

This area contains the LCD module interface registers (connector PL33). There are two register sets one enables the E0 strobe the other the E1 thus providing two multiplexed ports.

In addition there is a second mapping of the ROM which is write controlled, this allows for reprogramming of the flash in a safe way. Execution out of the flash while reprogramming is unlikely to succeed or yield correct results and is therefore not advised. The write control is performed using Bit 0 of the Board control register

Finally there are three board control registers directly implemented by the programmable support logic on the board implementing miscellaneous operations.

Region Start Address End Address Device
LCD Module 1 Registers 08000000 087FFFFF Write Command Register.
08800000 08FFFFFF Read Command Register.
09000000 097FFFFF Write Data Register.
09800000 09FFFFFF Read Data Register.
LCD Module 2 Registers 0A000000 0A7FFFFF Write Command Register.
0A800000 0AFFFFFF Read Command Register.
0B000000 0B7FFFFF Write Data Register.
0B800000 0BFFFFFF Read Data Register.
Alternate ROM mapping 0C000000 0DFFFFFF Write controlled Flash mapping.
Board Control Registers 0E000000 0E7FFFFF Control register 2.
0E800000 0EFFFFFF Control register 3.
0F000000 0F7FFFFF Control register 4
0F800000 0FFFFFFF Control register 5

External I/O

There are four regions all mapped to the same peripheral I/O however the four base regions have differing access types. The region starting at 0x10000000 when used as a base will read a single 8bit quantity from the peripheral using a slow cycle timing, whereas reading using a base of 0x28000000 would read 16bits from the peripheral with a fast cycle time.

The ASIX network controller and superio controller are optional and may not be fitted to all boards.

8 bit accesses to a single 8 bit wide register must occur in the 8 bit region and are on byte boundaries. (use LDRB STRB)

16 bit accesses must occur in the 16bit wide region and are on double byte boundaries. (use LDRH, STRH)

(multiple) 32 bit accesses may be made on either width regions and the access will be split into a series of incrementing addressed cycles. ie 4x8 bit cycles, 2x16 bit cycles. (Use LDR,STR) If LDM/STM is used, then multiples of these accesses will be performed until all data has been transferred. For any 32 bit width access, the initial address must always be word aligned.

As there is no additional hardware to support 8/16 bit IOCS16 signalling, it is incumbent on the user to use the correct transfer width (and memory offset) to match the width of the register being accessed.

The peripheral offsets into the four regions are as follows:

Offset Device
0x00000000 16MB ISA IO Space
0x01000000 ASIX AX88976 Network (NE2000 compatible)
0x01800000 PC Style Serial-IO Controller 1
0x02000000 Primary IDE channel standard register set
0x02800000 Primary IDE channel alternate register set
0x03000000 Secondary IDE channel standard register set
0x03800000 Secondary IDE channel alternate register set
0x04000000 16MB ISA Memory Space
0x05000000 Davicom DM9000 network controller

1The PC Style Serial-IO Controller can also appear in ISA IO space if CPLD configured to remap with Board Control Register 1

In addition there are some PC104 IRQ and Board control registers appear only in the fast region (0x28000000)

Address Register
2E000000 PC104 IRQ Status
2E800000 PC104 Raw IRQ
2F000000 PC104 IRQ Mask
2F800000 Board Control Register 1

S3C2410 I/O Special Function Registers

These peripherals are part of the S3C2410 itself and are always present.

Please refer to the Samsung S3C2410 datasheet for full details of all Special function registers.

Start Address End Address Device
48000000Memory Controller
49000000USB Host Controller
4A000000IRQ Controller
4B000000DMA Controller
4C000000Clock and Power Management
4D000000LCD Controller
4E000000NAND Flash
51000000PWM Timer
52000000USB Device
53000000Watchdog Timer
58000000A/D Converter
5A000000SD Interface

Board Control Registers (BCR)

These eight four bit registers are implemented to interface to various miscellaneous functions on the board. Three are primarily concerned with the IRQs from the PC104.

PC104 IRQ Status

Register address: 0x2E000000

0PC104 IRQ 3-
1PC104 IRQ 5-
2PC104 IRQ 7-
3PC104 IRQ 10-

PC104 Raw IRQ

Register address: 0x2E800000

0PC104 IRQ Pin 3-
1PC104 IRQ Pin 5-
2PC104 IRQ Pin 7-
3PC104 IRQ Pin 10-

PC104 IRQ Mask

Register address: 0x2F000000

0PC104 IRQ Mask 3PC104 IRQ Mask 3
1PC104 IRQ Mask 5PC104 IRQ Mask 5
2PC104 IRQ Mask 7PC104 IRQ Mask 7
3PC104 IRQ Mask 10PC104 IRQ Mask 10

Control Register 1

Register address: 0x2F800000

Control register 1 alters the mapping of the super I/O controller and controls the direction and routing of the I2S. See TI datasheet for meaning of lr0 and lr1.

3Super I/O remapSuper I/O remap

Control register 2

Register address: 0x0E000000

2NAND Write ProtectNAND Write Protect
3IDE ResetIDE Reset

Control register 3

Register address: 0x0E800000

NOR write enable and board ID.

0NOR ROM Write EnableNOR ROM Write Enable

Control register 4

Register address: 0x0F000000

This is the LCD module status register. The module is a relatively slow device and rather than hold the processor while I/O transactions complete an extended access method has been implemented.

LLAT is set during the first access to the byte-wide LCD module. When high, the previous control signals are latched until the LCD is accessed again. lcd_cmd, lcd_rw and lcde1 are the latched values of the LCD port. To access the LCD port, an operation must be done twice, with any data read from the first access being ignored. If LLAT is found to be high, this indicates that the LCD is mid-way through an access pair and requires the second access to complete. The held state can be deduced from the other bits so that an interrupted cycle can be resumed or safely aborted. The state of lcde2 is not(lcde1).


Control register 5

Register address: 0x0F800000

This is the DMA control register.

0 DMA Chanel 0 bit 0 DMA Chanel 0 bit 0
1 DMA Chanel 0 bit 1 DMA Chanel 0 bit 1
2 DMA Chanel 1 bit 0 DMA Chanel 1 bit 0
3 DMA Chanel 1 bit 1 DMA Chanel 1 bit 1

For both chanels the DMA is routed as:

Bit 0 Bit 1 Routing
0 0 Route to primary IDE 1
0 1 Route to secondary IDE 2
1 0 route to PC104 DMA1-5
1 1 route to PC104 DMA3-6

1Default for DMA channel 0.

2Default for DMA channel 1.

When DMA1 is the same value as DMA0 then all DMA is disabled.

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