Cirrus Logic PS7500FE SDRAM controller Introduction

The Cirrus Logic PS7500FE processor was designed to use Fast Page Mode (FPM) and Extended Data Out (EDO) memory devices. Memory technology has advanced and current Synchronous DRAM (SDRAM) devices are more cost effective. As a result, manufacturers are discontinuing the production of EDO devices, increasing the costs further.

In order to avoid this cost penalty and potential supply problem, this separate memory controller can be implemented in order to use standard SDRAM devices.

Hardware Description

This SDRAM Controller core can be fitted in a small CPLD, such as the Xilinx XC9572-5-VQ64 :

Usage
Feature	Usage	Usage (%)
Macrocells	43/72	59
Product Terms	204/360	56
Registers	18/72	25
Pins	52/52	100
Function Block Inputs	89/216	41

This SDRAM controller design supports :

• hardware SDRAM Command Operations
  • No Operation (NOP)
  • READ
  • WRITE
  • ACTIVE
  • PRECHARGE ALL
  • REFRESH and SELF REFRESH
  • LOAD MODE REGISTER (LMR)
  • SELF REFRESH POWER DOWN MODE
• Voltage level translation/buffering of the address lines using spare i/o pins
• 2 banks of SDRAM
• Mode Power down
• CAS Latency of 2
• Software programmable initialisation of SDRAM module
• Software programable decode for 32bit/64bit modules and 1/2 banks

Other pages

• Availability - Price and availability.
• Gallery - Images of the Cirrus Logic PS7500FE SDRAM controller.