EB7500ATX hardware reference document Authors (c) 2003 Simtec Electronics (BD, VS, GS) Version $Id: EB7500ATX-mmap.txt 177 2003-01-17 12:07:49Z vince $ Introduction This document explains the hardware memory layout of the EB7500ATX evaluation board by Simtec Electronics. The board includes the following IO devices for peripheral connectivity. * Crystal CS8920 10M Network controller * FDC37c669 PC SuperIO controller * Dallas DS1687 Realtime clock and NVRAM * ESS1879 Audio * DS1780 System monitoring * Power Management PIC (PMU) * Board control logic All addresses are shown in Hexadecimal unless otherwise specified. ARM7500 Memory map _______________________________________________________________ |Region______|Start_Address|End_Address|Device__________________| |ROM_________| |____________|00000000_____|00ffffff___|ROM_bank_0______________| |____________|01000000_____|01ffffff___|ROM_bank_1______________| |____________|02000000_____|02ffffff___|Reserved________________| |I/O_________| |____________|03000000_____|0300ffff___|Module_I/O_space________| |____________|03010000_____|0302bfff___|16MHz_PC_style_I/O______| |____________|0302c000_____|0302ffff___|Reserved________________| | |03030000 |0303ffff |Further module I/O space| |____________|_____________|___________|/tr>____________________| | |03040000 |031fffff |Reserved | |____________|_____________|___________|/tr>____________________| | |03200000 |0320ffff |CPU Registers (IOMD) | |____________|_____________|___________|/tr>____________________| | |03210000 |033fffff |Simple I/O space | |____________|_____________|___________|/tr>____________________| | |03400000 |034fffff |Video Register | |____________|_____________|___________|/tr>____________________| | |03500000 |03ffffff |Reserved | |____________|_____________|___________|/tr>____________________| | |04000000 |07ffffff |Reserved | |____________|_____________|___________|/tr>____________________| |Extended_I/O| | |08000000 |0fffffff |Extended I/O space | |____________|_____________|___________|/tr>____________________| |Memory______| | |10000000 |13ffffff |Dram bank 0 | |____________|_____________|___________|/tr>____________________| | |14000000 |17ffffff |Dram bank 1 | |____________|_____________|___________|/tr>____________________| | |18000000 |1bffffff |Dram bank 2 | |____________|_____________|___________|/tr>____________________| | |1c000000 |1fffffff |Dram bank 3 | |____________|_____________|___________|/tr>____________________| | |20000000 |ffffffff |ROM bank 0 (repeated) | |____________|_____________|___________|/tr>____________________| Regions ROM region The three ROM sockets on the motherboard are arranged in two banks. Bank 0 consists of the first two ROM sockets and may be configured as 32bits wide. Bank 1 is a single socket and may only be used in a 16Bit wide mode. The jumpers on PL12 may be used to swap the banks around or in conjunction with an optional FLASH SIMM, decode all 32 Mb of ROM address space to a single bank. See the EB7500ATX Technical reference manual for more details. I/O region All PC mapped i/o addresses are accessed on 4 byte boundaries i.e. their register offsets are value<<2 For a given PC i/o address, the appropriate ARM address can be found from 0x03010000 + (PC i/o address)<<2 Region Start Address End Address Device Module I/O space Unused - Access to this 03000000 0300ffff area will safely do nothing. 16MHz PC I/O (nCCS) 0301000 0300ffff 030101c8 AUX ID Register - memory timing 030101c0 DS1687 Address register 030101c4 DS1687 Data register 030101cc DS1687 Lock Register 030104f1 CS8920 PNP Low 03010600 03010640 CS8920 Default I/ O registers 030114f1 CS8920 PNP High 03014000 03016000 CS8920 Default Memory 03010fc0 37c669 SuperIO PNP address 03010fc4 37c669 SuperIO PNP data 030109e0 37c669 SuperIO LPT (0x278)1 030119e0 37c669 SuperIO EPP (LPT+0x400) 03010fe0 37c669 SuperIO COM1 (0x3f8) 03010be0 37c669 SuperIO COM2 (0x2f8) 03010fc0 37c669 SuperIO FDC (0x3f0) 03010800 ES1879 Audio game port 03010880 ES1879 Audio sound blaster 03010cc0 ES1879 Audio mpu401 03010e20 ES1879 Audio EM Synth 030114d0 ES1879 Audio WSS 03010e20 ES1879 Audio PP 03010ce0 ES1879 Audio CFG Base 16MHz PC I/O (nCDACK) 03012000 03029fff 03012000 37c669 FDC DMA 030120c0 ES1879 Audio play DMA 03012100 ES1879 Audio record DMA 030121c0 BCR - DRQ status 030121c4 BCR - ROM status 030121c8 BCR - DRQ interrupt enable 030121cc BCR - clock and system control 16MHz PC I/O (nCDACK TC) 0302a000 0302afff 16MHz PC I/O (nPCCS2) 0302b000 0302b7ff 16MHz PC I/O (nPCCS1) 0302b800 0302bfff 0302b800 0302bbff IDE channel 0 0302bc00 0302bfff IDE channel 1 Reserved 0302c000 0302ffff Unused Further module I/O space 03030000 0303ffff CPU Registers (IOMD) 03200000 0320ffff Simple I/O space 03210000 033fffff SOC Video and Sound 03400000 034fffff Extended I/O region This area is used for the ISA connector and supports 8 or 16bit accesses in either IO or Memory mode. Extended I/O 08000000 0bffffff ISA Slot I/O space /tr> 0c000000 0fffffff ISA Slot Memory space /tr> PC style ISA address may be converted to this areas addressing scheme by multiplying by 4 and adding the appropriate offset for either IO or Memory accesses. i.e. For a given PC ISA i/o address, the appropriate ARM address can be found from: 0x08000000 + (PC i/o address)<<2 Similarly, the PC ISA memory address can be found from: 0x0c000000 + (PC memory address)<<2 Use LDRB and STRB instructions for 8bit accesses and LDR or STR instructions to generate 16bit accesses (note upper 16bits will be discarded on write and undefined on read) IRQ Mappings IRQ Source 7500 IRQ Function ISA Slot 10 IOP4 ISA Slot 7 IOP5 ISA Slot 5 IOP6 ISA Slot 3 IOP7 CS8920 IRQ 3 INT5 DS1687 RTC IOP3 (shared) Dallas system monitor IOP3 (shared) IDE channel 0 nEvent1 IDE channel 1 nEvent2 ESS1879 IRQ9 (C) INT3 ESS1879 IRQ7 (B) INT8 37c669 Serial 1 INT6 37c669 Serial 2 INT7 37c669 FDC INT4 37c669 Printer INT2 37c669 FDC Index INT1 PS2 PS2 Keyboard is connected to the 7500s PS2 keyboard interface, and the PS2 mouse is connected to the 7500s mouse interface. Network Crystal Semiconductor (Cirrus Logic) CS8920, with wake-on-lan support and supports both IO and Memory map accesses. The CS8920 PNP address should be configured for ISA base at 0x300 to achieve the default register mapping as specified. Note memory addresses are all have bit 23 tied high in hardware. This only effects the value programmed into the CS8920 memory offset registers. Network DRQ is connected to DRQ5 Super IO 37c669 providing two serial, one parallel port and a floppy disc controller. The addresses shown in the memory map assume the pnp base registers are programmed as shown. It is advised these not be changed or conflicts may occur as the various chip selects for the on-board peripherals are hardware decoded to unique address ranges. This prevents access conflicts between the various on-board peripherals due to incorrect PnP resource allocation. DMA request A is connected to the printer dma channel DMA request B is connected to the FDC DMA channel * IRQ F is conencted to FDC IRQ * IRQ E is connected to IRQ printer * IRQ D is connected to IRQ serial 1 * IRQ C is connected to IRQ serial 2 * IRQ A is connected to IRQ ECP System Monitoring The PSU and FAN connector are monitored by an Dallas DS1780 chip, connected to either the I2C or DDC bus (DDC is the standard configuration). The A0 and A1 pins are grounded, and the IRQ is connected to the IOP3 pin on the 7500. The monitored inputs are: Input Monitoring Notes Vccp1 fuse alarm readings <150 indicate tripped fuse 2.5v 5v sby 3.3v not used 5v 5v main supply 12v +12v supply -vccp2 -12v supply vd0 user settable link cap on PL22. vd1 user settable link cap on PL22. vd2 user settable link cap on PL22. vd3 keyboard fuse state 1=ok 0=trip vd4 midi supply fuse state 1=ok 0=trip The ADC output is buffered and feeds a single 0-10v fan supply for accurate fan speed control. The fan tacho feedback is routed to then FAN1 input. FAN2 is not used. I2C The I2C bus is connected to the 7500 open-drain pins and is implemented in software. * OD0 I2C Clock * OD1 I2C Data. DDC The DDC signals from the VGA port are connected to the IOP inputs * DDC Clock is connected to IOP1 * DDC Data is connected to IOP2 These signals are only enabled when the DDC enable is configured in the board control registers. This prevents external DDC traffic from interfering with internal DDC communication between PIC, system monitor and 7500. The PMU PIC is connected to this bus. RTC Device is a Dallas DS1687. The RS hardware additionally has a RTC Lock register which must be written to before the RTC data port can be accessed. The lock is automatically applied each time the address port is accessed and must be cleared before the data port can be used. To read a value from the RTC: * write address to address register * write anything to the lock register * read data byte from data register To write a value to the RTC: * write address to address register * write anything to the lock register * write data byte to the data register The IRQ is shared with the Dallas RTC. IDE Two IDE ports are fitted, each with registers spaced 0x40 bytes apart with the extra control register at offset 0x380 from the base of the port. PIO timings can be changed by modifying the access speed register in the IOMD, as there is nothing else in the nPCCS1 space. The Reset line is asserted by clearing bit 4 in BCR clock and system control register, and may be read back to check the current state of the IDE reset line. This will read 0 if the IDE reset line is stuck low - E.G. the IDE cable has been reversed. Sound The sound support is provided by an ESS ES1879, mapped into the nCCS space. The I2S from the 7500 is fed to the IISCLK and IIDATA pins for the ES chip to digitise and mix. For correct operation with the ESS, the 7500's I2S format register at 320006c should be set to "normal" (bit 1=0) The chip will need the relevant PnP information programming before it can be used * DRQ0 is connected to the play DMA * DRQ1 is connected to the record DMA It is recommended that sound playback is routed via the 7500's I2S DMA hardware and recording performed using PIO on the ESS through the substantial 256 byte PIO buffer. Board Control Registers(BCR) 030101c8: AUX ID register - memory timings bits 8..9: dram bank 0 timing [read only] bits 10..11: dram bank 1 timing [read only] note, these values are from the identification lines on the SIMMs themselves, and may not necessarily be valid. 030121c0: DRQ status [read only] bit 0: FDC bit 1: PRN (EPP/ECP DMA transfer mode) bit 2: CS8920 NET (receive) bit 3: ESS1879 Play bit 4: ESS1879 Record 030121c4: ROM status [read only] bit 0 = romsel0 (see PL12 in the hardware manual) bit 1 = romsel1 bit 2 = romsel2 - 1=global ROM write enable, 0=global ROM write protect bit 3: 0 = rom space write protected 1 = rom space write unprotected 030121c8: DRQ interrupt enable [ read / write ] bit 0: FDC bit 1: PRN (? printer) bit 2: CS8920 bit 3: ESS1879 Play bit 4: ESS1870 Record default is for bit 0 set, all others clear 030121cc: clock and system control ___________________________________________________________________________ |bit|description______________________|notes________________________________| | |00 = 56MHz memory clock |This controls the oscillator feeding | |0-1|01 = 64MHz memory clock |the memory clock input on the 7500 | | |10 = 72MHz memory clock |for 80 MHz memory clock 50ns EDO DRAM| |___|11_=_80MHz_memory_clock__________|is_essential_________________________| | |High voltage generator enable for|Links 12 and 15 must be set correctly| |2 |on-board flash programming. |to enable programming (as standard, | |___|_________________________________|links_not_fitted).___________________| | | |( 1 = DDC enabled, 0 = DDC disabled) | | | |This bit controls whether the DDC bus| | | |is connected to the DDC pins on the | | | |VGA port for use with an external | | | |monitor. | |3 |External DDC Mux control |This bit also enables high voltage | | | |programming to the power management | | | |PIC for in-circuit programming. An | | | |additional programming link must also| | | |be fitted so use of this signal is | |___|_________________________________|safe.________________________________| |4 |IDE Reset |write (0=assert, 1=de-assert), | |___|_________________________________|read=state_of_reset_pin._____________|