EB7500ATX hardware reference document

Authors(c) 2003 Simtec Electronics (BD, VS, GS)
Version$Id: EB7500ATX-mmap.html 221 2003-02-20 16:34:45Z vince $


This document explains the hardware memory layout of the EB7500ATX evaluation board by Simtec Electronics. The board includes the following IO devices for peripheral connectivity.

All addresses are shown in Hexadecimal unless otherwise specified.

ARM7500 Memory map

RegionStart AddressEnd AddressDevice
0000000000ffffffROM bank 0
0100000001ffffffROM bank 1
030000000300ffffModule I/O space
030100000302bfff16MHz PC style I/O
030300000303ffffFurther module I/O space
032000000320ffffCPU Registers (IOMD)
03210000033fffffSimple I/O space
03400000034fffffVideo Register
Extended I/O
080000000fffffffExtended I/O space
1000000013ffffffDram bank 0
1400000017ffffffDram bank 1
180000001bffffffDram bank 2
1c0000001fffffffDram bank 3
20000000ffffffffROM bank 0 (repeated)


ROM region

The three ROM sockets on the motherboard are arranged in two banks. Bank 0 consists of the first two ROM sockets and may be configured as 32bits wide. Bank 1 is a single socket and may only be used in a 16Bit wide mode. The jumpers on PL12 may be used to swap the banks around or in conjunction with an optional FLASH SIMM, decode all 32 Mb of ROM address space to a single bank. See the EB7500ATX Technical reference manual for more details.

I/O region

All PC mapped i/o addresses are accessed on 4 byte boundaries i.e. their register offsets are value<<2

For a given PC i/o address, the appropriate ARM address can be found from 0x03010000 + (PC i/o address)<<2
RegionStart AddressEnd AddressDevice
Module I/O space
030000000300ffffUnused - Access to this area will safely do nothing.
16MHz PC I/O (nCCS)03010000300ffff
030101c8AUX ID Register - memory timing
030101c0DS1687 Address register
030101c4DS1687 Data register
030101ccDS1687 Lock Register
030104f1CS8920 PNP Low
0301060003010640CS8920 Default I/O registers
030114f1CS8920 PNP High
0301400003016000CS8920 Default Memory
03010fc037c669 SuperIO PNP address
03010fc437c669 SuperIO PNP data
030109e037c669 SuperIO LPT (0x278)1
030119e037c669 SuperIO EPP (LPT+0x400)
03010fe037c669 SuperIO COM1 (0x3f8)
03010be037c669 SuperIO COM2 (0x2f8)
03010fc037c669 SuperIO FDC (0x3f0)
03010800ES1879 Audio game port
03010880ES1879 Audio sound blaster
03010cc0ES1879 Audio mpu401
03010e20ES1879 Audio EM Synth
030114d0ES1879 Audio WSS
03010e20ES1879 Audio PP
03010ce0ES1879 Audio CFG Base
16MHz PC I/O (nCDACK)0301200003029fff
0301200037c669 FDC DMA
030120c0ES1879 Audio play DMA
03012100ES1879 Audio record DMA
030121c0BCR - DRQ status
030121c4BCR - ROM status
030121c8BCR - DRQ interrupt enable
030121ccBCR - clock and system control
16MHz PC I/O (nCDACK TC)0302a0000302afff
16MHz PC I/O (nPCCS2)0302b0000302b7ff
16MHz PC I/O (nPCCS1)0302b8000302bfff
0302b8000302bbffIDE channel 0
0302bc000302bfffIDE channel 1
Further module I/O space
CPU Registers (IOMD)
Simple I/O space
SOC Video and Sound

Extended I/O region

This area is used for the ISA connector and supports 8 or 16bit accesses in either IO or Memory mode.
Extended I/O
080000000bffffffISA Slot I/O space
0c0000000fffffffISA Slot Memory space

PC style ISA address may be converted to this areas addressing scheme by multiplying by 4 and adding the appropriate offset for either IO or Memory accesses. i.e.

For a given PC ISA i/o address, the appropriate ARM address can be found from:
0x08000000 + (PC i/o address)<<2
Similarly, the PC ISA memory address can be found from:
0x0c000000 + (PC memory address)<<2

Use LDRB and STRB instructions for 8bit accesses and LDR or STR instructions to generate 16bit accesses (note upper 16bits will be discarded on write and undefined on read)

IRQ Mappings

IRQ Source 7500 IRQ Function
ISA Slot 10IOP4
ISA Slot 7IOP5
ISA Slot 5IOP6
ISA Slot 3IOP7
CS8920 IRQ 3INT5
DS1687 RTCIOP3 (shared)
Dallas system monitorIOP3 (shared)
IDE channel 0nEvent1
IDE channel 1nEvent2
ESS1879 IRQ9 (C)INT3
ESS1879 IRQ7 (B)INT8
37c669 Serial 1INT6
37c669 Serial 2INT7
37c669 FDC INT4
37c669 Printer INT2
37c669 FDC IndexINT1


PS2 Keyboard is connected to the 7500s PS2 keyboard interface, and the PS2 mouse is connected to the 7500s mouse interface.


Crystal Semiconductor (Cirrus Logic) CS8920, with wake-on-lan support and supports both IO and Memory map accesses.

The CS8920 PNP address should be configured for ISA base at 0x300 to achieve the default register mapping as specified.

Note memory addresses are all have bit 23 tied high in hardware. This only effects the value programmed into the CS8920 memory offset registers.

Network DRQ is connected to DRQ5

Super IO

37c669 providing two serial, one parallel port and a floppy disc controller.

The addresses shown in the memory map assume the pnp base registers are programmed as shown. It is advised these not be changed or conflicts may occur as the various chip selects for the on-board peripherals are hardware decoded to unique address ranges. This prevents access conflicts between the various on-board peripherals due to incorrect PnP resource allocation.

DMA request A is connected to the printer dma channel

DMA request B is connected to the FDC DMA channel

System Monitoring

The PSU and FAN connector are monitored by an Dallas DS1780 chip, connected to either the I2C or DDC bus (DDC is the standard configuration). The A0 and A1 pins are grounded, and the IRQ is connected to the IOP3 pin on the 7500.

The monitored inputs are:
Vccp1fuse alarmreadings <150 indicate tripped fuse
2.5v5v sby
3.3vnot used
5v5v main supply
12v+12v supply
-vccp2-12v supply
vd0user settable link cap on PL22.
vd1user settable link cap on PL22.
vd2user settable link cap on PL22.
vd3keyboard fuse state 1=ok 0=trip
vd4midi supply fuse state 1=ok 0=trip

The ADC output is buffered and feeds a single 0-10v fan supply for accurate fan speed control. The fan tacho feedback is routed to then FAN1 input. FAN2 is not used.


The I2C bus is connected to the 7500 open-drain pins and is implemented in software.


The DDC signals from the VGA port are connected to the IOP inputs

These signals are only enabled when the DDC enable is configured in the board control registers. This prevents external DDC traffic from interfering with internal DDC communication between PIC, system monitor and 7500.

The PMU PIC is connected to this bus.


Device is a Dallas DS1687.

The RS hardware additionally has a RTC Lock register which must be written to before the RTC data port can be accessed. The lock is automatically applied each time the address port is accessed and must be cleared before the data port can be used.

To read a value from the RTC:

To write a value to the RTC:

The IRQ is shared with the Dallas RTC.


Two IDE ports are fitted, each with registers spaced 0x40 bytes apart with the extra control register at offset 0x380 from the base of the port.

PIO timings can be changed by modifying the access speed register in the IOMD, as there is nothing else in the nPCCS1 space.

The Reset line is asserted by clearing bit 4 in BCR clock and system control register, and may be read back to check the current state of the IDE reset line. This will read 0 if the IDE reset line is stuck low - E.G. the IDE cable has been reversed.


The sound support is provided by an ESS ES1879, mapped into the nCCS space.

The I2S from the 7500 is fed to the IISCLK and IIDATA pins for the ES chip to digitise and mix. For correct operation with the ESS, the 7500's I2S format register at 320006c should be set to "normal" (bit 1=0)

The chip will need the relevant PnP information programming before it can be used

It is recommended that sound playback is routed via the 7500's I2S DMA hardware and recording performed using PIO on the ESS through the substantial 256 byte PIO buffer.

Board Control Registers(BCR)

030101c8: AUX ID register - memory timings

bits 8..9: dram bank 0 timing [read only]
bits 10..11: dram bank 1 timing [read only]

note, these values are from the identification lines on the SIMMs themselves, and may not necessarily be valid.

030121c0: DRQ status [read only]

bit 0: FDC
bit 1: PRN (EPP/ECP DMA transfer mode)
bit 2: CS8920 NET (receive)
bit 3: ESS1879 Play
bit 4: ESS1879 Record

030121c4: ROM status [read only]

bit 0 = romsel0 (see PL12 in the hardware manual) bit 1 = romsel1 bit 2 = romsel2 - 1=global ROM write enable, 0=global ROM write protect

bit 3: 0 = rom space write protected
1 = rom space write unprotected

030121c8: DRQ interrupt enable [ read / write ]

bit 0: FDC
bit 1: PRN (? printer)
bit 2: CS8920
bit 3: ESS1879 Play
bit 4: ESS1870 Record

default is for bit 0 set, all others clear

030121cc: clock and system control

0-1 00 = 56MHz memory clock
01 = 64MHz memory clock
10 = 72MHz memory clock
11 = 80MHz memory clock
This controls the oscillator feeding the memory clock input on the 7500
for 80 MHz memory clock 50ns EDO DRAM is essential
2High voltage generator enable for on-board flash programming.Links 12 and 15 must be set correctly to enable programming (as standard, links not fitted).
3 External DDC Mux control ( 1 = DDC enabled, 0 = DDC disabled)
This bit controls whether the DDC bus is connected to the DDC pins on the VGA port for use with an external monitor.
This bit also enables high voltage programming to the power management PIC for in-circuit programming. An additional programming link must also be fitted so use of this signal is safe.
4 IDE Reset write (0=assert, 1=de-assert), read=state of reset pin.