|Authors||(c) 2003 Simtec Electronics (BD, VS, GS)|
|Version||$Id: EB7500ATX-mmap.html 221 2003-02-20 16:34:45Z vince $|
This document explains the hardware memory layout of the EB7500ATX evaluation board by Simtec Electronics. The board includes the following IO devices for peripheral connectivity.
All addresses are shown in Hexadecimal unless otherwise specified.
|Region||Start Address||End Address||Device|
|00000000||00ffffff||ROM bank 0|
|01000000||01ffffff||ROM bank 1|
|03000000||0300ffff||Module I/O space|
|03010000||0302bfff||16MHz PC style I/O|
|03030000||0303ffff||Further module I/O space|
|03200000||0320ffff||CPU Registers (IOMD)|
|03210000||033fffff||Simple I/O space|
|08000000||0fffffff||Extended I/O space|
|10000000||13ffffff||Dram bank 0|
|14000000||17ffffff||Dram bank 1|
|18000000||1bffffff||Dram bank 2|
|1c000000||1fffffff||Dram bank 3|
|20000000||ffffffff||ROM bank 0 (repeated)|
The three ROM sockets on the motherboard are arranged in two
banks. Bank 0 consists of the first two ROM sockets and may be
configured as 32bits wide. Bank 1 is a single socket and may only be
used in a 16Bit wide mode. The jumpers on PL12 may be used to swap the
banks around or in conjunction with an optional FLASH SIMM, decode all
32 Mb of ROM address space to a single bank. See the EB7500ATX
Technical reference manual for more details.
All PC mapped i/o addresses are accessed on 4 byte boundaries i.e. their register offsets are value<<2
For a given PC i/o address, the appropriate ARM address can be found from 0x03010000 + (PC i/o address)<<2
|Region||Start Address||End Address||Device|
|Module I/O space|
|03000000||0300ffff||Unused - Access to this area will safely do nothing.|
|16MHz PC I/O (nCCS)||0301000||0300ffff|
|030101c8||AUX ID Register - memory timing|
|030101c0||DS1687 Address register|
|030101c4||DS1687 Data register|
|030101cc||DS1687 Lock Register|
|030104f1||CS8920 PNP Low|
|03010600||03010640||CS8920 Default I/O registers|
|030114f1||CS8920 PNP High|
|03014000||03016000||CS8920 Default Memory|
|03010fc0||37c669 SuperIO PNP address|
|03010fc4||37c669 SuperIO PNP data|
|030109e0||37c669 SuperIO LPT (0x278)1|
|030119e0||37c669 SuperIO EPP (LPT+0x400)|
|03010fe0||37c669 SuperIO COM1 (0x3f8)|
|03010be0||37c669 SuperIO COM2 (0x2f8)|
|03010fc0||37c669 SuperIO FDC (0x3f0)|
|03010800||ES1879 Audio game port|
|03010880||ES1879 Audio sound blaster|
|03010cc0||ES1879 Audio mpu401|
|03010e20||ES1879 Audio EM Synth|
|030114d0||ES1879 Audio WSS|
|03010e20||ES1879 Audio PP|
|03010ce0||ES1879 Audio CFG Base|
|16MHz PC I/O (nCDACK)||03012000||03029fff|
|03012000||37c669 FDC DMA|
|030120c0||ES1879 Audio play DMA|
|03012100||ES1879 Audio record DMA|
|030121c0||BCR - DRQ status|
|030121c4||BCR - ROM status|
|030121c8||BCR - DRQ interrupt enable|
|030121cc||BCR - clock and system control|
|16MHz PC I/O (nCDACK TC)||0302a000||0302afff|
|16MHz PC I/O (nPCCS2)||0302b000||0302b7ff|
|16MHz PC I/O (nPCCS1)||0302b800||0302bfff|
|0302b800||0302bbff||IDE channel 0|
|0302bc00||0302bfff||IDE channel 1|
|Further module I/O space|
|CPU Registers (IOMD)|
|Simple I/O space|
|SOC Video and Sound|
This area is used for the ISA connector and supports 8 or 16bit accesses in either IO or Memory mode.
|08000000||0bffffff||ISA Slot I/O space|
|0c000000||0fffffff||ISA Slot Memory space|
PC style ISA address may be converted to this areas addressing scheme by multiplying by 4 and adding the appropriate offset for either IO or Memory accesses. i.e.
For a given PC ISA i/o address, the appropriate ARM address can be found from:
0x08000000 + (PC i/o address)<<2
Similarly, the PC ISA memory address can be found from:
0x0c000000 + (PC memory address)<<2
Use LDRB and STRB instructions for 8bit accesses and LDR or STR instructions to generate 16bit accesses (note upper 16bits will be discarded on write and undefined on read)
|IRQ Source||7500 IRQ Function|
|ISA Slot 10||IOP4|
|ISA Slot 7||IOP5|
|ISA Slot 5||IOP6|
|ISA Slot 3||IOP7|
|CS8920 IRQ 3||INT5|
|DS1687 RTC||IOP3 (shared)|
|Dallas system monitor||IOP3 (shared)|
|IDE channel 0||nEvent1|
|IDE channel 1||nEvent2|
|ESS1879 IRQ9 (C)||INT3|
|ESS1879 IRQ7 (B)||INT8|
|37c669 Serial 1||INT6|
|37c669 Serial 2||INT7|
|37c669 FDC Index||INT1|
PS2 Keyboard is connected to the 7500s PS2 keyboard interface, and the PS2 mouse is connected to the 7500s mouse interface.
Crystal Semiconductor (Cirrus Logic) CS8920, with wake-on-lan support and supports both IO and Memory map accesses.
The CS8920 PNP address should be configured for ISA base at 0x300 to achieve the default register mapping as specified.
Note memory addresses are all have bit 23 tied high in hardware. This only effects the value programmed into the CS8920 memory offset registers.
Network DRQ is connected to DRQ5
37c669 providing two serial, one parallel port and a floppy disc controller.
The addresses shown in the memory map assume the pnp base registers are programmed as shown. It is advised these not be changed or conflicts may occur as the various chip selects for the on-board peripherals are hardware decoded to unique address ranges. This prevents access conflicts between the various on-board peripherals due to incorrect PnP resource allocation.
DMA request A is connected to the printer dma channel
DMA request B is connected to the FDC DMA channel
The PSU and FAN connector are monitored by an Dallas DS1780 chip, connected to either the I2C or DDC bus (DDC is the standard configuration). The A0 and A1 pins are grounded, and the IRQ is connected to the IOP3 pin on the 7500.
The monitored inputs are:
|Vccp1||fuse alarm||readings <150 indicate tripped fuse|
|5v||5v main supply|
|vd0||user settable link cap on PL22.|
|vd1||user settable link cap on PL22.|
|vd2||user settable link cap on PL22.|
|vd3||keyboard fuse state 1=ok 0=trip|
|vd4||midi supply fuse state 1=ok 0=trip|
The ADC output is buffered and feeds a single 0-10v fan supply for accurate fan speed control. The fan tacho feedback is routed to then FAN1 input. FAN2 is not used.
The I2C bus is connected to the 7500 open-drain pins and is implemented in software.
The DDC signals from the VGA port are connected to the IOP inputs
These signals are only enabled when the DDC enable is configured in the board control registers. This prevents external DDC traffic from interfering with internal DDC communication between PIC, system monitor and 7500.
The PMU PIC is connected to this bus.
Device is a Dallas DS1687.
The RS hardware additionally has a RTC Lock register which must be written to before the RTC data port can be accessed. The lock is automatically applied each time the address port is accessed and must be cleared before the data port can be used.
To read a value from the RTC:
To write a value to the RTC:
The IRQ is shared with the Dallas RTC.
Two IDE ports are fitted, each with registers spaced 0x40 bytes apart with the extra control register at offset 0x380 from the base of the port.
PIO timings can be changed by modifying the access speed register in the IOMD, as there is nothing else in the nPCCS1 space.
The Reset line is asserted by clearing bit 4 in BCR clock and system control register, and may be read back to check the current state of the IDE reset line. This will read 0 if the IDE reset line is stuck low - E.G. the IDE cable has been reversed.
The sound support is provided by an ESS ES1879, mapped into the nCCS space.
The I2S from the 7500 is fed to the IISCLK and IIDATA pins for the ES chip to digitise and mix. For correct operation with the ESS, the 7500's I2S format register at 320006c should be set to "normal" (bit 1=0)
The chip will need the relevant PnP information programming before it can be used
It is recommended that sound playback is routed via the 7500's I2S DMA hardware and recording performed using PIO on the ESS through the substantial 256 byte PIO buffer.
bits 8..9: dram bank 0 timing [read only]
bits 10..11: dram bank 1 timing [read only]
note, these values are from the identification lines on the SIMMs themselves, and may not necessarily be valid.
bit 0: FDC
bit 1: PRN (EPP/ECP DMA transfer mode)
bit 2: CS8920 NET (receive)
bit 3: ESS1879 Play
bit 4: ESS1879 Record
bit 3: 0 = rom space write protected
1 = rom space write unprotected
bit 0: FDC
bit 1: PRN (? printer)
bit 2: CS8920
bit 3: ESS1879 Play
bit 4: ESS1870 Record
default is for bit 0 set, all others clear
030121cc: clock and system control
|0-1||00 = 56MHz memory clock
01 = 64MHz memory clock
10 = 72MHz memory clock
11 = 80MHz memory clock
|This controls the oscillator feeding the memory clock input on the
for 80 MHz memory clock 50ns EDO DRAM is essential
|2||High voltage generator enable for on-board flash programming.||Links 12 and 15 must be set correctly to enable programming (as standard, links not fitted).|
|3||External DDC Mux control||( 1 = DDC enabled, 0 = DDC disabled)
This bit controls whether the DDC bus is connected to the DDC pins on the VGA port for use with an external monitor.
This bit also enables high voltage programming to the power management PIC for in-circuit programming. An additional programming link must also be fitted so use of this signal is safe.
|4||IDE Reset||write (0=assert, 1=de-assert), read=state of reset pin.|