FB1 FB2 FB3 FB4

Signal Name	Total Product Terms	Product Terms	Location	Power Mode	Pin Number	PinType	Pin Use
nSync	1	1_1	MC1	STD	87	I/O	O
(unused)	0		MC2		94	I/O
ShiftClk	1	3_1	MC3	STD	91	I/O	O
(unused)	0		MC4		93	I/O
pix_count<0>	1	5_1	MC5	STD	95	I/O	(b)
ShiftClk_int	1	6_1	MC6	STD	96	I/O	(b)
HorizCount<0>	1	7_1	MC7	STD	3	I/O/GTS1	(b)
CPUAccessOn/CPUAccessOn_RSTF__$INT	1	8_1	MC8	STD	97	I/O	(b)
pix_count<2>	2	9_1 9_2	MC9	STD	99	I/O/GSR	GSR/I
pix_count<1>	2	10_1 10_2	MC10	STD	1	I/O	(b)
IntWait/IntWait_RSTF	2	10_3 10_4	MC11	STD	4	I/O/GTS2	(b)
(unused)	0		MC12		6	I/O	(b)
nSync_BUFR	23	11_1 11_2 11_3 11_4 11_5 12_1 12_2 12_3 12_4 12_5 13_1 13_2 13_3 13_4 13_5 14_1 14_2 14_3 14_4 14_5 15_3 15_4 15_5	MC13	STD	8	I/O	I
(unused)	0		MC14		9	I/O	(b)
D<7>	2	15_1 15_2	MC15	STD	11	I/O	I/O
IntWait	2	16_1 16_2	MC16	STD	10	I/O	(b)
D<6>	2	17_1 17_2	MC17	STD	12	I/O	I/O
ShiftLoad	2	18_1 18_2	MC18	STD	92	I/O	O

Signals Used By Logic in Function Block

1. A0
2. Addr<10>
3. Addr<1>
4. Addr<2>
5. Addr<3>
6. Addr<4>
7. Addr<5>
8. Addr<6>
9. Addr<7>
10. Addr<8>
11. Addr<9>
12. CPUAccessOn
13. CPUAccessStrobe
14. Clk
15. RamD<6>.PIN
16. RamD<7>.PIN
17. HorizClk
18. HorizCount<0>
19. IntWait/IntWait_RSTF
20. ReloadReady
21. ShiftClk_int
22. VertState_FFd1
23. VertState_FFd2
24. nCS
25. nOE
26. nRst
27. nSync_BUFR
28. pix_count<0>
29. pix_count<1>