# Timing Report

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Design Name | main
Device, Speed (SpeedFile Version) | XC9572XL, -7 (3.0)
Date Created | Tue Feb 07 10:44:13 2006
Created By | Timing Report Generator: version H.42
Copyright | Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.

## Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period | 13.000 ns.
Max. Clock Frequency (fSYSTEM) | 76.923 MHz.
Limited by Clock Pulse Width for nCS
Clock to Setup (tCYC) | 8.800 ns.
Pad to Pad Delay (tPD) | 14.800 ns.
Setup to Clock at the Pad (tSU) | 0.700 ns.
Clock Pad to Output Pad Delay (tCO) | 34.000 ns.

## Timing Constraints

Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing
--- | --- | --- | --- | ---
TS1000 | 0.0 | 0.0 | 0 | 0
TS1001 | 0.0 | 0.0 | 0 | 0
TS1002 | 0.0 | 0.0 | 0 | 0
TS1003 | 0.0 | 0.0 | 0 | 0
TS1004 | 0.0 | 0.0 | 0 | 0
AUTO_TS_F2F | 0.0 | 8.8 | 233 | 233
AUTO_TS_P2P | 0.0 | 34.0 | 134 | 134
AUTO_TS_P2F | 0.0 | 7.1 | 7 | 7
AUTO_TS_F2P | 0.0 | 16.5 | 90 | 90

### Constraint: TS1000

Description: PERIOD:PERIOD_nCS:0.000 nS
Path | Requirement (ns) | Delay (ns) | Slack (ns)
--- | --- | --- | ---

### Constraint: TS1001

Description: PERIOD:PERIOD_CPUAccess.Q:0.000 nS
Path | Requirement (ns) | Delay (ns) | Slack (ns)
--- | --- | --- | ---

### Constraint: TS1002

Description: PERIOD:PERIOD_Clk:0.000 nS
Path | Requirement (ns) | Delay (ns) | Slack (ns)
--- | --- | --- | ---

### Constraint: TS1003

Description: PERIOD:PERIOD_ShiftClk_int.Q:0.000 nS
Path | Requirement (ns) | Delay (ns) | Slack (ns)
--- | --- | --- | ---

### Constraint: TS1004

Description: PERIOD:PERIOD_HorizClk.Q:0.000 nS
Path | Requirement (ns) | Delay (ns) | Slack (ns)
--- | --- | --- | ---

### Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path | Requirement (ns) | Delay (ns) | Slack (ns)
--- | --- | --- | ---
Addr<10>.Q to Addr<7>.D | 0.000 | 8.800 | -8.800
Addr<11>.Q to Addr<7>.D | 0.000 | 8.800 | -8.800
Addr<12>.Q to Addr<7>.D | 0.000 | 8.800 | -8.800

### Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path | Requirement (ns) | Delay (ns) | Slack (ns)
--- | --- | --- | ---
Clk to nSync | 0.000 | 34.000 | -34.000
Clk to BufEn | 0.000 | 28.700 | -28.700
Clk to D<0> | 0.000 | 28.700 | -28.700

### Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path | Requirement (ns) | Delay (ns) | Slack (ns)
--- | --- | --- | ---
nRst to ReloadAccess.D | 0.000 | 7.100 | -7.100
nRst to ReloadReady.D | 0.000 | 7.100 | -7.100
nRst to HorizClk.CE | 0.000 | 6.300 | -6.300

### Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path | Requirement (ns) | Delay (ns) | Slack (ns)
--- | --- | --- | ---
Addr<10>.Q to nSync | 0.000 | 16.500 | -16.500
Addr<1>.Q to nSync | 0.000 | 16.500 | -16.500
Addr<2>.Q to nSync | 0.000 | 16.500 | -16.500

Number of constraints not met: 4

## Data Sheet Report

### Maximum External Clock Speeds

Clock | fEXT (MHz) | Reason
--- | --- | ---
nCS | 76.923 | Limited by Clock Pulse Width for nCS
CPUAccess.Q | 76.923 | Limited by Clock Pulse Width for CPUAccess.Q
Clk | 76.923 | Limited by Clock Pulse Width for Clk
ShiftClk_int.Q | 76.923 | Limited by Clock Pulse Width for ShiftClk_int.Q
HorizClk.Q | 76.923 | Limited by Clock Pulse Width for HorizClk.Q

### Setup/Hold Times for Clocks

Setup/Hold Times for Clock ShiftClk_int.Q
Source Pad | Setup to clk (edge) | Hold to clk (edge)
--- | --- | ---
nRst | 0.700 | 2.300

### Clock to Pad Timing

Clock nCS to Pad
Destination Pad | Clock (edge) to Pad
--- | ---
xWait | 13.900

Clock Clk to Pad
Destination Pad | Clock (edge) to Pad
--- | ---
nSync | 34.000
BufEn | 28.700
D<0> | 28.700
D<10> | 28.700
D<11> | 28.700
D<12> | 28.700
D<13> | 28.700
D<14> | 28.700
D<15> | 28.700
D<1> | 28.700
D<2> | 28.700
D<3> | 28.700
D<4> | 28.700
D<5> | 28.700
D<6> | 28.700
D<7> | 28.700
D<8> | 28.700
D<9> | 28.700
RamD<0> | 28.700
RamD<1> | 28.700
RamD<2> | 28.700
RamD<3> | 28.700
RamD<4> | 28.700
RamD<5> | 28.700
RamD<6> | 28.700
RamD<7> | 28.700
SA0 | 28.700
nBlank | 27.500
RamOE | 26.700
RamWE | 26.700
ShiftClk | 26.700
Addr<10> | 22.300
Addr<11> | 22.300
Addr<12> | 22.300
Addr<13> | 22.300
Addr<14> | 22.300
Addr<1> | 22.300
Addr<2> | 22.300
Addr<3> | 22.300
Addr<4> | 22.300
Addr<5> | 22.300
Addr<6> | 22.300
Addr<7> | 22.300
Addr<8> | 22.300
Addr<9> | 22.300
ShiftLoad | 7.700

### Clock to Setup Times for Clocks

Clock to Setup for clock CPUAccess.Q
Source | Destination | Delay
--- | --- | ---
CPUAccessOn.Q | CPUAccessOn.CE | 8.000

Clock to Setup for clock ShiftClk_int.Q
Source | Destination | Delay
--- | --- | ---
ReloadAccess.Q | ReloadAccess.D | 8.800
ReloadReady.Q | ReloadReady.D | 8.800
pix_count<0>.Q | ReloadAccess.D | 8.800
pix_count<0>.Q | ReloadReady.D | 8.800
pix_count<1>.Q | ReloadAccess.D | 8.800
pix_count<1>.Q | ReloadReady.D | 8.800
pix_count<2>.Q | ReloadAccess.D | 8.800
pix_count<2>.Q | ReloadReady.D | 8.800
CPUAccess.Q | CPUAccess.D | 8.000
CPUAccessStrobe.Q | CPUAccessStrobe.D | 8.000
HorizClk.Q | HorizClk.D | 8.000
pix_count<0>.Q | CPUAccess.D | 8.000
pix_count<0>.Q | CPUAccessStrobe.D | 8.000
pix_count<0>.Q | HorizClk.D | 8.000
pix_count<0>.Q | pix_count<1>.D | 8.000
pix_count<0>.Q | pix_count<2>.D | 8.000
pix_count<1>.Q | CPUAccess.D | 8.000
pix_count<1>.Q | CPUAccessStrobe.D | 8.000
pix_count<1>.Q | HorizClk.D | 8.000
pix_count<1>.Q | pix_count<2>.D | 8.000
pix_count<2>.Q | CPUAccess.D | 8.000
pix_count<2>.Q | CPUAccessStrobe.D | 8.000
pix_count<2>.Q | HorizClk.D | 8.000

Clock to Setup for clock HorizClk.Q
Source | Destination | Delay
--- | --- | ---
Addr<10>.Q | Addr<7>.D | 8.800
Addr<11>.Q | Addr<7>.D | 8.800
Addr<12>.Q | Addr<7>.D | 8.800
Addr<13>.Q | Addr<7>.D | 8.800
Addr<14>.Q | Addr<7>.D | 8.800
Addr<7>.Q | Addr<7>.D | 8.800
Addr<8>.Q | Addr<7>.D | 8.800
Addr<9>.Q | Addr<7>.D | 8.800
VertCount<8>.Q | Addr<7>.D | 8.800
VertState_FFd1.Q | Addr<7>.D | 8.800
VertState_FFd2.Q | Addr<7>.D | 8.800
Addr<10>.Q | Addr<10>.D | 8.000
Addr<10>.Q | Addr<11>.D | 8.000
Addr<10>.Q | Addr<12>.D | 8.000
Addr<10>.Q | Addr<13>.D | 8.000
Addr<10>.Q | Addr<14>.D | 8.000
Addr<10>.Q | VertCount<8>.D | 8.000
Addr<10>.Q | VertState_FFd1.D | 8.000
Addr<10>.Q | VertState_FFd2.D | 8.000
Addr<11>.Q | Addr<10>.D | 8.000
Addr<11>.Q | Addr<11>.D | 8.000
Addr<11>.Q | Addr<12>.D | 8.000
Addr<11>.Q | Addr<13>.D | 8.000
Addr<11>.Q | Addr<14>.D | 8.000
Addr<11>.Q | VertCount<8>.D | 8.000
Addr<11>.Q | VertState_FFd1.D | 8.000
Addr<11>.Q | VertState_FFd2.D | 8.000
Addr<12>.Q | Addr<10>.D | 8.000
Addr<12>.Q | Addr<11>.D | 8.000
Addr<12>.Q | Addr<12>.D | 8.000
Addr<12>.Q | Addr<13>.D | 8.000
Addr<12>.Q | Addr<14>.D | 8.000
Addr<12>.Q | VertCount<8>.D | 8.000
Addr<12>.Q | VertState_FFd1.D | 8.000
Addr<12>.Q | VertState_FFd2.D | 8.000
Addr<13>.Q | Addr<10>.D | 8.000
Addr<13>.Q | Addr<11>.D | 8.000
Addr<13>.Q | Addr<12>.D | 8.000
Addr<13>.Q | Addr<14>.D | 8.000
Addr<13>.Q | VertCount<8>.D | 8.000
Addr<13>.Q | VertState_FFd1.D | 8.000
Addr<13>.Q | VertState_FFd2.D | 8.000
Addr<14>.Q | Addr<10>.D | 8.000
Addr<14>.Q | Addr<11>.D | 8.000
Addr<14>.Q | Addr<12>.D | 8.000
Addr<14>.Q | VertCount<8>.D | 8.000
Addr<14>.Q | VertState_FFd1.D | 8.000
Addr<14>.Q | VertState_FFd2.D | 8.000
Addr<1>.Q | Addr<10>.CE | 8.000
Addr<1>.Q | Addr<11>.CE | 8.000
Addr<1>.Q | Addr<12>.CE | 8.000
Addr<1>.Q | Addr<13>.CE | 8.000
Addr<1>.Q | Addr<14>.CE | 8.000
Addr<1>.Q | Addr<2>.D | 8.000
Addr<1>.Q | Addr<3>.D | 8.000
Addr<1>.Q | Addr<4>.D | 8.000
Addr<1>.Q | Addr<5>.D | 8.000
Addr<1>.Q | Addr<6>.D | 8.000
Addr<1>.Q | Addr<7>.CE | 8.000
Addr<1>.Q | Addr<8>.CE | 8.000
Addr<1>.Q | Addr<9>.CE | 8.000
Addr<1>.Q | VertCount<8>.CE | 8.000
Addr<1>.Q | VertState_FFd1.CE | 8.000
Addr<1>.Q | VertState_FFd2.CE | 8.000
Addr<2>.Q | Addr<10>.CE | 8.000
Addr<2>.Q | Addr<11>.CE | 8.000
Addr<2>.Q | Addr<12>.CE | 8.000
Addr<2>.Q | Addr<13>.CE | 8.000
Addr<2>.Q | Addr<14>.CE | 8.000
Addr<2>.Q | Addr<3>.D | 8.000
Addr<2>.Q | Addr<4>.D | 8.000
Addr<2>.Q | Addr<5>.D | 8.000
Addr<2>.Q | Addr<6>.D | 8.000
Addr<2>.Q | Addr<7>.CE | 8.000
Addr<2>.Q | Addr<8>.CE | 8.000
Addr<2>.Q | Addr<9>.CE | 8.000
Addr<2>.Q | VertCount<8>.CE | 8.000
Addr<2>.Q | VertState_FFd1.CE | 8.000
Addr<2>.Q | VertState_FFd2.CE | 8.000
Addr<3>.Q | Addr<10>.CE | 8.000
Addr<3>.Q | Addr<11>.CE | 8.000
Addr<3>.Q | Addr<12>.CE | 8.000
Addr<3>.Q | Addr<13>.CE | 8.000
Addr<3>.Q | Addr<14>.CE | 8.000
Addr<3>.Q | Addr<4>.D | 8.000
Addr<3>.Q | Addr<5>.D | 8.000
Addr<3>.Q | Addr<6>.D | 8.000
Addr<3>.Q | Addr<7>.CE | 8.000
Addr<3>.Q | Addr<8>.CE | 8.000
Addr<3>.Q | Addr<9>.CE | 8.000
Addr<3>.Q | VertCount<8>.CE | 8.000
Addr<3>.Q | VertState_FFd1.CE | 8.000
Addr<3>.Q | VertState_FFd2.CE | 8.000
Addr<4>.Q | Addr<10>.CE | 8.000
Addr<4>.Q | Addr<11>.CE | 8.000
Addr<4>.Q | Addr<12>.CE | 8.000
Addr<4>.Q | Addr<13>.CE | 8.000
Addr<4>.Q | Addr<14>.CE | 8.000
Addr<4>.Q | Addr<5>.D | 8.000
Addr<4>.Q | Addr<6>.D | 8.000
Addr<4>.Q | Addr<7>.CE | 8.000
Addr<4>.Q | Addr<8>.CE | 8.000
Addr<4>.Q | Addr<9>.CE | 8.000
Addr<4>.Q | VertCount<8>.CE | 8.000
Addr<4>.Q | VertState_FFd1.CE | 8.000
Addr<4>.Q | VertState_FFd2.CE | 8.000
Addr<5>.Q | Addr<10>.CE | 8.000
Addr<5>.Q | Addr<11>.CE | 8.000
Addr<5>.Q | Addr<12>.CE | 8.000
Addr<5>.Q | Addr<13>.CE | 8.000
Addr<5>.Q | Addr<14>.CE | 8.000
Addr<5>.Q | Addr<6>.D | 8.000
Addr<5>.Q | Addr<7>.CE | 8.000
Addr<5>.Q | Addr<8>.CE | 8.000
Addr<5>.Q | Addr<9>.CE | 8.000
Addr<5>.Q | VertCount<8>.CE | 8.000
Addr<5>.Q | VertState_FFd1.CE | 8.000
Addr<5>.Q | VertState_FFd2.CE | 8.000
Addr<6>.Q | Addr<10>.CE | 8.000
Addr<6>.Q | Addr<11>.CE | 8.000
Addr<6>.Q | Addr<12>.CE | 8.000
Addr<6>.Q | Addr<13>.CE | 8.000
Addr<6>.Q | Addr<14>.CE | 8.000
Addr<6>.Q | Addr<7>.CE | 8.000
Addr<6>.Q | Addr<8>.CE | 8.000
Addr<6>.Q | Addr<9>.CE | 8.000
Addr<6>.Q | VertCount<8>.CE | 8.000
Addr<6>.Q | VertState_FFd1.CE | 8.000
Addr<6>.Q | VertState_FFd2.CE | 8.000
Addr<7>.Q | Addr<10>.D | 8.000
Addr<7>.Q | Addr<11>.D | 8.000
Addr<7>.Q | Addr<12>.D | 8.000
Addr<7>.Q | Addr<13>.D | 8.000
Addr<7>.Q | Addr<14>.D | 8.000
Addr<7>.Q | Addr<8>.D | 8.000
Addr<7>.Q | Addr<9>.D | 8.000
Addr<7>.Q | VertCount<8>.D | 8.000
Addr<7>.Q | VertState_FFd1.D | 8.000
Addr<7>.Q | VertState_FFd2.D | 8.000
Addr<8>.Q | Addr<10>.D | 8.000
Addr<8>.Q | Addr<11>.D | 8.000
Addr<8>.Q | Addr<12>.D | 8.000
Addr<8>.Q | Addr<13>.D | 8.000
Addr<8>.Q | Addr<14>.D | 8.000
Addr<8>.Q | Addr<9>.D | 8.000
Addr<8>.Q | VertCount<8>.D | 8.000
Addr<8>.Q | VertState_FFd1.D | 8.000
Addr<8>.Q | VertState_FFd2.D | 8.000
Addr<9>.Q | Addr<10>.D | 8.000
Addr<9>.Q | Addr<11>.D | 8.000
Addr<9>.Q | Addr<12>.D | 8.000
Addr<9>.Q | Addr<13>.D | 8.000
Addr<9>.Q | Addr<14>.D | 8.000
Addr<9>.Q | VertCount<8>.D | 8.000
Addr<9>.Q | VertState_FFd1.D | 8.000
Addr<9>.Q | VertState_FFd2.D | 8.000
HorizCount<0>.Q | Addr<10>.CE | 8.000
HorizCount<0>.Q | Addr<11>.CE | 8.000
HorizCount<0>.Q | Addr<12>.CE | 8.000
HorizCount<0>.Q | Addr<13>.CE | 8.000
HorizCount<0>.Q | Addr<14>.CE | 8.000
HorizCount<0>.Q | Addr<1>.D | 8.000
HorizCount<0>.Q | Addr<2>.D | 8.000
HorizCount<0>.Q | Addr<3>.D | 8.000
HorizCount<0>.Q | Addr<4>.D | 8.000
HorizCount<0>.Q | Addr<5>.D | 8.000
HorizCount<0>.Q | Addr<6>.D | 8.000
HorizCount<0>.Q | Addr<7>.CE | 8.000
HorizCount<0>.Q | Addr<8>.CE | 8.000
HorizCount<0>.Q | Addr<9>.CE | 8.000
HorizCount<0>.Q | VertCount<8>.CE | 8.000
HorizCount<0>.Q | VertState_FFd1.CE | 8.000
HorizCount<0>.Q | VertState_FFd2.CE | 8.000
VertCount<8>.Q | Addr<10>.D | 8.000
VertCount<8>.Q | Addr<11>.D | 8.000
VertCount<8>.Q | Addr<12>.D | 8.000
VertCount<8>.Q | VertCount<8>.D | 8.000
VertCount<8>.Q | VertState_FFd1.D | 8.000
VertCount<8>.Q | VertState_FFd2.D | 8.000
VertState_FFd1.Q | Addr<10>.D | 8.000
VertState_FFd1.Q | Addr<11>.D | 8.000
VertState_FFd1.Q | Addr<12>.D | 8.000
VertState_FFd1.Q | VertCount<8>.D | 8.000
VertState_FFd1.Q | VertState_FFd1.D | 8.000
VertState_FFd1.Q | VertState_FFd2.D | 8.000
VertState_FFd2.Q | Addr<10>.D | 8.000
VertState_FFd2.Q | Addr<11>.D | 8.000
VertState_FFd2.Q | Addr<12>.D | 8.000
VertState_FFd2.Q | VertCount<8>.D | 8.000
VertState_FFd2.Q | VertState_FFd1.D | 8.000
VertState_FFd2.Q | VertState_FFd2.D | 8.000

### Pad to Pad List

Source Pad | Destination Pad | Delay
--- | --- | ---
nRst | nSync | 14.800
A0 | D<0> | 9.500
A0 | D<10> | 9.500
A0 | D<11> | 9.500
A0 | D<12> | 9.500
A0 | D<13> | 9.500
A0 | D<14> | 9.500
A0 | D<15> | 9.500
A0 | D<1> | 9.500
A0 | D<2> | 9.500
A0 | D<3> | 9.500
A0 | D<4> | 9.500
A0 | D<5> | 9.500
A0 | D<6> | 9.500
A0 | D<7> | 9.500
A0 | D<8> | 9.500
A0 | D<9> | 9.500
nOE | D<0> | 9.500
nOE | D<10> | 9.500
nOE | D<11> | 9.500
nOE | D<12> | 9.500
nOE | D<13> | 9.500
nOE | D<14> | 9.500
nOE | D<15> | 9.500
nOE | D<1> | 9.500
nOE | D<2> | 9.500
nOE | D<3> | 9.500
nOE | D<4> | 9.500
nOE | D<5> | 9.500
nOE | D<6> | 9.500
nOE | D<7> | 9.500
nOE | D<8> | 9.500
nOE | D<9> | 9.500
nWE | RamD<0> | 9.500
nWE | RamD<1> | 9.500
nWE | RamD<2> | 9.500
nWE | RamD<3> | 9.500
nWE | RamD<4> | 9.500
nWE | RamD<5> | 9.500
nWE | RamD<6> | 9.500
nWE | RamD<7> | 9.500
A0 | RamD<0> | 8.300
A0 | RamD<4> | 8.300
D<0> | RamD<0> | 8.300
D<12> | RamD<4> | 8.300
D<4> | RamD<4> | 8.300
D<8> | RamD<0> | 8.300
A0 | RamD<1> | 7.500
A0 | RamD<2> | 7.500
A0 | RamD<3> | 7.500
A0 | RamD<5> | 7.500
A0 | RamD<6> | 7.500
A0 | RamD<7> | 7.500
A0 | SA0 | 7.500
D<10> | RamD<2> | 7.500
D<11> | RamD<3> | 7.500
D<13> | RamD<5> | 7.500
D<14> | RamD<6> | 7.500
D<15> | RamD<7> | 7.500
D<1> | RamD<1> | 7.500
D<2> | RamD<2> | 7.500
D<3> | RamD<3> | 7.500
D<5> | RamD<5> | 7.500
D<6> | RamD<6> | 7.500
D<7> | RamD<7> | 7.500
D<9> | RamD<1> | 7.500
RamD<0> | D<0> | 7.500
RamD<0> | D<8> | 7.500
RamD<1> | D<1> | 7.500
RamD<1> | D<9> | 7.500
RamD<2> | D<10> | 7.500
RamD<2> | D<2> | 7.500
RamD<3> | D<11> | 7.500
RamD<3> | D<3> | 7.500
RamD<4> | D<12> | 7.500
RamD<4> | D<4> | 7.500
RamD<5> | D<13> | 7.500
RamD<5> | D<5> | 7.500
RamD<6> | D<14> | 7.500
RamD<6> | D<6> | 7.500
RamD<7> | D<15> | 7.500
RamD<7> | D<7> | 7.500
nCS | xWait | 7.500
nOE | RamOE | 7.500
nRst | nBlank | 7.500
nWE | RamWE | 7.500
nWait_in | xWait | 7.500

Number of paths analyzed: 464
Number of Timing errors: 464
Analysis Completed: Tue Feb 07 10:44:13 2006