### Failure Table

Signal Name | FB1 | FB2 | FB3 | FB4
--- | --- | --- | --- | ---

Legend:
ce - signal clock enable cannot be placed
clk - signal clock cannot be placed
fbi - insufficient function block inputs available to place signal
io - insufficient I/O pins available to place output
loc - signal cannot be placed in this FB because it is assigned to a different FB
mc - insufficient macrocells available to place signal
oe - signal output enable cannot be placed
pt - insufficient product terms available to place signal
sr - signal set/reset cannot be placed
unk - unknown reason for failure - Please contact Xilinx Support