    cpldfit:  version H.42                              Xilinx Inc.
                                      Fitter Report
    Design Name: main                                Date:  2- 7-2006, 10:44AM
    Device Used: XC9572XL-7-TQ100
    Fitting Status: Successful

    *************************  Mapped Resource Summary  **************************

    Macrocells     Product Terms    Function Block   Registers      Pins
    Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot
    66 /72  ( 92%) 228 /360  ( 63%) 130/216 ( 60%)   30 /72  ( 42%) 55 /72  ( 76%)

    ** Function Block Resources **

    Function    Mcells      FB Inps     Pterms      IO
    Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot
    FB1          18/18*      32/54       55/90      12/18
    FB2          14/18       29/54       43/90       5/18
    FB3          16/18       27/54       54/90      13/18
    FB4          18/18*      42/54       76/90      18/18*
                 -----       -----       -----      -----
                 66/72      130/216     228/360     48/72

    * - Resource is exhausted

    ** Global Control Resources **

    Global clock net(s) unused.
    Global output enable net(s) unused.
    Signal 'nRst' mapped onto global set/reset net GSR.

    ** Pin Resources **

    Signal Type    Required     Mapped  |  Pin Type            Used    Total
    ------------------------------------|------------------------------------
    Input         :    6           6    |  I/O              :    52      66
    Output        :   24          24    |  GCK/IO           :     2       3
    Bidirectional :   24          24    |  GTS/IO           :     0       2
    GCK           :    0           0    |  GSR/IO           :     1       1
    GTS           :    0           0    |
    GSR           :    1           1    |
                     ----        ----
            Total     55          55

    ** Power Data **

    There are 66 macrocells in high performance mode (MCHP).
    There are 0 macrocells in low power mode (MCLP).
    End of Mapped Resource Summary
    **************************  Errors and Warnings  ***************************

    WARNING:Cpld:896 - Unable to map all desired signals into function block, FB2,
       because too many function block product terms are required. Buffering output
       signal nSync to allow all signals assigned to this function block to be
       placed.
    *************************  Summary of Mapped Logic  ************************

    ** 48 Outputs **

    Signal                              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
    Name                                Pts   Inps          No.  Type    Use     Mode Rate State
    D<2>                                2     4     FB1_1   16   I/O     I/O     STD  FAST
    D<5>                                2     4     FB1_2   13   I/O     I/O     STD  FAST
    D<0>                                2     4     FB1_3   18   I/O     I/O     STD  FAST
    D<4>                                2     4     FB1_5   14   I/O     I/O     STD  FAST
    D<3>                                2     4     FB1_6   15   I/O     I/O     STD  FAST
    xWait                               2     3     FB1_7   25   I/O     O       STD  FAST
    D<1>                                2     4     FB1_8   17   I/O     I/O     STD  FAST
    BufEn                               1     2     FB1_10  28   I/O     O       STD  FAST
    D<8>                                2     4     FB1_12  33   I/O     I/O     STD  FAST
    D<10>                               2     4     FB1_13  36   I/O     I/O     STD  FAST
    D<12>                               2     4     FB1_16  39   I/O     I/O     STD  FAST
    D<13>                               2     4     FB1_18  40   I/O     I/O     STD  FAST
    nSync                               1     1     FB2_1   87   I/O     O       STD  FAST
    ShiftClk                            1     4     FB2_3   91   I/O     O       STD  FAST
    D<7>                                2     4     FB2_15  11   I/O     I/O     STD  FAST
    D<6>                                2     4     FB2_17  12   I/O     I/O     STD  FAST
    ShiftLoad                           2     2     FB2_18  92   I/O     O       STD  FAST RESET
    D<14>                               2     4     FB3_1   41   I/O     I/O     STD  FAST
    D<9>                                2     4     FB3_5   35   I/O     I/O     STD  FAST
    SA0                                 3     4     FB3_7   54   I/O     O       STD  FAST
    D<11>                               2     4     FB3_8   37   I/O     I/O     STD  FAST
    D<15>                               2     4     FB3_9   42   I/O     I/O     STD  FAST
    Addr<5>                             3     7     FB3_10  60   I/O     O       STD  FAST RESET
    Addr<4>                             3     6     FB3_12  61   I/O     O       STD  FAST RESET
    Addr<13>                            4     15    FB3_13  63   I/O     O       STD  FAST RESET
    Addr<8>                             4     10    FB3_14  55   I/O     O       STD  FAST RESET
    Addr<7>                             6     20    FB3_15  56   I/O     O       STD  FAST RESET
    Addr<3>                             3     5     FB3_16  64   I/O     O       STD  FAST RESET
    Addr<6>                             3     8     FB3_17  58   I/O     O       STD  FAST RESET
    Addr<14>                            4     16    FB3_18  59   I/O     O       STD  FAST RESET
    Addr<12>                            5     20    FB4_1   65   I/O     O       STD  FAST RESET
    Addr<11>                            5     20    FB4_2   67   I/O     O       STD  FAST RESET
    RamD<7>                             5     5     FB4_3   71   I/O     I/O     STD  FAST
    Addr<9>                             4     11    FB4_4   72   I/O     O       STD  FAST RESET
    Addr<1>                             3     3     FB4_5   68   I/O     O       STD  FAST RESET
    RamD<6>                             5     5     FB4_6   76   I/O     I/O     STD  FAST
    RamD<3>                             5     5     FB4_7   77   I/O     I/O     STD  FAST
    Addr<10>                            5     20    FB4_8   70   I/O     O       STD  FAST RESET
    Addr<2>                             3     4     FB4_9   66   I/O     O       STD  FAST RESET
    RamD<2>                             5     5     FB4_10  81   I/O     I/O     STD  FAST

    Signal                              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
    Name                                Pts   Inps          No.  Type    Use     Mode Rate State
    RamD<5>                             5     5     FB4_11  74   I/O     I/O     STD  FAST
    nBlank                              8     10    FB4_12  82   I/O     O       STD  FAST
    RamD<0>                             5     5     FB4_13  85   I/O     I/O     STD  FAST
    RamD<4>                             5     5     FB4_14  78   I/O     I/O     STD  FAST
    RamCE                               0     0     FB4_15  89   I/O     O       STD  FAST
    RamWE                               1     3     FB4_16  86   I/O     O       STD  FAST
    RamOE                               2     4     FB4_17  90   I/O     O       STD  FAST
    RamD<1>                             5     5     FB4_18  79   I/O     I/O     STD  FAST

    ** 18 Buried Nodes **

    Signal                              Total Total Loc     Pwr  Reg Init
    Name                                Pts   Inps          Mode State
    CPUAccessStrobe                     3     5     FB1_4   STD  RESET
    CPUAccessOn                         3     3     FB1_9   STD  RESET
    CPUAccess                           3     5     FB1_11  STD  RESET
    ReloadAccess                        9     15    FB1_14  STD  RESET
    HorizClk                            4     6     FB1_15  STD  RESET
    ReloadReady                         10    15    FB1_17  STD  RESET
    pix_count<0>                        1     1     FB2_5   STD  RESET
    ShiftClk_int                        1     1     FB2_6   STD  RESET
    HorizCount<0>                       1     1     FB2_7   STD  RESET
    CPUAccessOn/CPUAccessOn_RSTF__$INT  1     2     FB2_8   STD
    pix_count<2>                        2     3     FB2_9   STD  RESET
    pix_count<1>                        2     2     FB2_10  STD  RESET
    IntWait/IntWait_RSTF                2     3     FB2_11  STD
    nSync_BUFR                          23    14    FB2_13  STD
    IntWait                             2     2     FB2_16  STD  RESET
    VertState_FFd2                      4     19    FB3_2   STD  RESET
    VertState_FFd1                      4     19    FB3_3   STD  RESET
    VertCount<8>                        5     19    FB3_4   STD  RESET

    ** 7 Inputs **

    Signal                              Loc     Pin  Pin     Pin
    Name                                        No.  Type    Use
    nWait_in                            FB1_4   20   I/O     I
    nWE                                 FB1_9   22   GCK/I/O I
    nOE                                 FB1_11  23   GCK/I/O I
    nCS                                 FB1_15  29   I/O     I
    nRst                                FB2_9   99   GSR/I/O GSR/I
    Clk                                 FB2_13  8    I/O     I
    A0                                  FB3_3   49   I/O     I

    Legend:
    Pin No. - ~ - User Assigned
    **************************  Function Block Details  ************************
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X            - Signal used as input to the macrocell logic.
    Pin No.      - ~  - User Assigned
    *********************************** FB1  ***********************************
    Number of function block inputs used/remaining:               32/22
    Number of signals used by logic mapping into function block:  32
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    D<2>                  2       0     0   3     FB1_1   16    I/O     I/O
    D<5>                  2       0     0   3     FB1_2   13    I/O     I/O
    D<0>                  2       0     0   3     FB1_3   18    I/O     I/O
    CPUAccessStrobe       3       0     0   2     FB1_4   20    I/O     I
    D<4>                  2       0     0   3     FB1_5   14    I/O     I/O
    D<3>                  2       0     0   3     FB1_6   15    I/O     I/O
    xWait                 2       0     0   3     FB1_7   25    I/O     O
    D<1>                  2       0     0   3     FB1_8   17    I/O     I/O
    CPUAccessOn           3       0     0   2     FB1_9   22    GCK/I/O I
    BufEn                 1       0     0   4     FB1_10  28    I/O     O
    CPUAccess             3       0     0   2     FB1_11  23    GCK/I/O I
    D<8>                  2       0     0   3     FB1_12  33    I/O     I/O
    D<10>                 2       0   \/3   0     FB1_13  36    I/O     I/O
    ReloadAccess          9       4<-   0   0     FB1_14  27    GCK/I/O (b)
    HorizClk              4       0   /\1   0     FB1_15  29    I/O     I
    D<12>                 2       0   \/2   1     FB1_16  39    I/O     I/O
    ReloadReady          10       5<-   0   0     FB1_17  30    I/O     (b)
    D<13>                 2       0   /\3   0     FB1_18  40    I/O     I/O

    Signals Used by Logic in Function Block
      1: A0                                  12: RamD<2>.PIN       23: ShiftClk_int
      2: Addr<1>                             13: RamD<3>.PIN       24: VertState_FFd1
      3: Addr<2>                             14: RamD<4>.PIN       25: VertState_FFd2
      4: Addr<3>                             15: RamD<5>.PIN       26: nCS
      5: Addr<4>                             16: RamD<0>.PIN       27: nOE
      6: Addr<5>                             17: RamD<1>.PIN       28: nRst
      7: Addr<6>                             18: HorizClk          29: nWait_in
      8: CPUAccess                           19: HorizCount<0>     30: pix_count<0>
      9: CPUAccessOn                         20: IntWait           31: pix_count<1>
     10: CPUAccessOn/CPUAccessOn_RSTF__$INT  21: ReloadAccess      32: pix_count<2>
     11: CPUAccessStrobe                     22: ReloadReady

    Signal                        1         2         3         4 FB
    Name                0----+----0----+----0----+----0----+----0 Inputs
    D<2>                 X.......X..X..............X............. 4
    D<5>                 X.......X.....X...........X............. 4
    D<0>                 X.......X......X..........X............. 4
    CPUAccessStrobe      ..........X...........X......XXX........ 5
    D<4>                 X.......X....X............X............. 4
    D<3>                 X.......X...X.............X............. 4
    xWait                ...................X.....X..X........... 3
    D<1>                 X.......X.......X.........X............. 4
    CPUAccessOn          .......XXX.............................. 3
    BufEn                .......XX............................... 2
    CPUAccess            .......X..............X......XXX........ 5
    D<8>                 X.......X......X..........X............. 4
    D<10>                X.......X..X..............X............. 4
    ReloadAccess         .XXXXXX...........X.X.XXX..X.XXX........ 15
    HorizClk             .................X....X....X.XXX........ 6
    D<12>                X.......X....X............X............. 4
    ReloadReady          .XXXXXX...........X..XXXX..X.XXX........ 15
    D<13>                X.......X.....X...........X............. 4
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *********************************** FB2  ***********************************
    Number of function block inputs used/remaining:               29/25
    Number of signals used by logic mapping into function block:  29
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    nSync                 1       0     0   4     FB2_1   87    I/O     O
    (unused)              0       0     0   5     FB2_2   94    I/O
    ShiftClk              1       0     0   4     FB2_3   91    I/O     O
    (unused)              0       0     0   5     FB2_4   93    I/O
    pix_count<0>          1       0     0   4     FB2_5   95    I/O     (b)
    ShiftClk_int          1       0     0   4     FB2_6   96    I/O     (b)
    HorizCount<0>         1       0     0   4     FB2_7   3     GTS/I/O (b)
    CPUAccessOn/CPUAccessOn_RSTF__$INT
                          1       0     0   4     FB2_8   97    I/O     (b)
    pix_count<2>          2       0     0   3     FB2_9   99    GSR/I/O GSR/I
    pix_count<1>          2       0   \/2   1     FB2_10  1     I/O     (b)
    IntWait/IntWait_RSTF
                          2       2<- \/5   0     FB2_11  4     GTS/I/O (b)
    (unused)              0       0   \/5   0     FB2_12  6     I/O     (b)
    nSync_BUFR           23      18<-   0   0     FB2_13  8     I/O     I
    (unused)              0       0   /\5   0     FB2_14  9     I/O     (b)
    D<7>                  2       0   /\3   0     FB2_15  11    I/O     I/O
    IntWait               2       0     0   3     FB2_16  10    I/O     (b)
    D<6>                  2       0     0   3     FB2_17  12    I/O     I/O
    ShiftLoad             2       0     0   3     FB2_18  92    I/O     O

    Signals Used by Logic in Function Block
      1: A0                11: Addr<9>               21: ShiftClk_int
      2: Addr<10>          12: CPUAccessOn           22: VertState_FFd1
      3: Addr<1>           13: CPUAccessStrobe       23: VertState_FFd2
      4: Addr<2>           14: Clk                   24: nCS
      5: Addr<3>           15: RamD<6>.PIN           25: nOE
      6: Addr<4>           16: RamD<7>.PIN           26: nRst
      7: Addr<5>           17: HorizClk              27: nSync_BUFR
      8: Addr<6>           18: HorizCount<0>         28: pix_count<0>
      9: Addr<7>           19: IntWait/IntWait_RSTF  29: pix_count<1>
     10: Addr<8>           20: ReloadReady

    Signal                        1         2         3         4 FB
    Name                0----+----0----+----0----+----0----+----0 Inputs
    nSync                ..........................X............. 1
    ShiftClk             ...................XXXX................. 4
    pix_count<0>         ....................X................... 1
    ShiftClk_int         .............X.......................... 1
    HorizCount<0>        ................X....................... 1
    CPUAccessOn/CPUAccessOn_RSTF__$INT
                         .......................X.X.............. 2
    pix_count<2>         ....................X......XX........... 3
    pix_count<1>         ....................X......X............ 2
    IntWait/IntWait_RSTF
                         ...........XX............X.............. 3
    nSync_BUFR           .XXXXXXXXXX......X...XX..X.............. 14
    D<7>                 X..........X...X........X............... 4
    IntWait              ..................X....X................ 2
    D<6>                 X..........X..X.........X............... 4
    ShiftLoad            .............X.....X.................... 2
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *********************************** FB3  ***********************************
    Number of function block inputs used/remaining:               27/27
    Number of signals used by logic mapping into function block:  27
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    D<14>                 2       0     0   3     FB3_1   41    I/O     I/O
    VertState_FFd2        4       0     0   1     FB3_2   32    I/O     (b)
    VertState_FFd1        4       0     0   1     FB3_3   49    I/O     I
    VertCount<8>          5       0     0   0     FB3_4   50    I/O     (b)
    D<9>                  2       0     0   3     FB3_5   35    I/O     I/O
    (unused)              0       0     0   5     FB3_6   53    I/O
    SA0                   3       0     0   2     FB3_7   54    I/O     O
    D<11>                 2       0     0   3     FB3_8   37    I/O     I/O
    D<15>                 2       0     0   3     FB3_9   42    I/O     I/O
    Addr<5>               3       0     0   2     FB3_10  60    I/O     O
    (unused)              0       0     0   5     FB3_11  52    I/O
    Addr<4>               3       0     0   2     FB3_12  61    I/O     O
    Addr<13>              4       0     0   1     FB3_13  63    I/O     O
    Addr<8>               4       0   \/1   0     FB3_14  55    I/O     O
    Addr<7>               6       1<-   0   0     FB3_15  56    I/O     O
    Addr<3>               3       0     0   2     FB3_16  64    I/O     O
    Addr<6>               3       0     0   2     FB3_17  58    I/O     O
    Addr<14>              4       0     0   1     FB3_18  59    I/O     O

    Signals Used by Logic in Function Block
      1: A0                10: Addr<4>           19: RamD<7>.PIN
      2: Addr<10>          11: Addr<5>           20: RamD<1>.PIN
      3: Addr<11>          12: Addr<6>           21: HorizClk
      4: Addr<12>          13: Addr<7>           22: HorizCount<0>
      5: Addr<13>          14: Addr<8>           23: ReloadAccess
      6: Addr<14>          15: Addr<9>           24: VertCount<8>
      7: Addr<1>           16: CPUAccessOn       25: VertState_FFd1
      8: Addr<2>           17: RamD<3>.PIN       26: VertState_FFd2
      9: Addr<3>           18: RamD<6>.PIN       27: nOE

    Signal                        1         2         3         4 FB
    Name                0----+----0----+----0----+----0----+----0 Inputs
    D<14>                X..............X.X........X............. 4
    VertState_FFd2       .XXXXXXXXXXXXXX.....XX.XXX.............. 19
    VertState_FFd1       .XXXXXXXXXXXXXX.....XX.XXX.............. 19
    VertCount<8>         .XXXXXXXXXXXXXX.....XX.XXX.............. 19
    D<9>                 X..............X...X......X............. 4
    SA0                  X..............X.....XX................. 4
    D<11>                X..............XX.........X............. 4
    D<15>                X..............X..X.......X............. 4
    Addr<5>              ......XXXX..........XXX................. 7
    Addr<4>              ......XXX...........XXX................. 6
    Addr<13>             .XXX..XXXXXXXXX.....XXX................. 15
    Addr<8>              ......XXXXXXX.......XXX................. 10
    Addr<7>              .XXXXXXXXXXXXXX.....XXXXXX.............. 20
    Addr<3>              ......XX............XXX................. 5
    Addr<6>              ......XXXXX.........XXX................. 8
    Addr<14>             .XXXX.XXXXXXXXX.....XXX................. 16
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *********************************** FB4  ***********************************
    Number of function block inputs used/remaining:               42/12
    Number of signals used by logic mapping into function block:  42
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    Addr<12>              5       0     0   0     FB4_1   65    I/O     O
    Addr<11>              5       0     0   0     FB4_2   67    I/O     O
    RamD<7>               5       0     0   0     FB4_3   71    I/O     I/O
    Addr<9>               4       0     0   1     FB4_4   72    I/O     O
    Addr<1>               3       0     0   2     FB4_5   68    I/O     O
    RamD<6>               5       0     0   0     FB4_6   76    I/O     I/O
    RamD<3>               5       0     0   0     FB4_7   77    I/O     I/O
    Addr<10>              5       0     0   0     FB4_8   70    I/O     O
    Addr<2>               3       0     0   2     FB4_9   66    I/O     O
    RamD<2>               5       0     0   0     FB4_10  81    I/O     I/O
    RamD<5>               5       0     0   0     FB4_11  74    I/O     I/O
    nBlank                8       3<-   0   0     FB4_12  82    I/O     O
    RamD<0>               5       3<- /\3   0     FB4_13  85    I/O     I/O
    RamD<4>               5       3<- /\3   0     FB4_14  78    I/O     I/O
    RamCE                 0       0   /\3   2     FB4_15  89    I/O     O
    RamWE                 1       0     0   4     FB4_16  86    I/O     O
    RamOE                 2       0     0   3     FB4_17  90    I/O     O
    RamD<1>               5       0     0   0     FB4_18  79    I/O     I/O

    Signals Used by Logic in Function Block
      1: A0                15: Addr<9>           29: D<4>.PIN
      2: Addr<10>          16: CPUAccessOn       30: D<5>.PIN
      3: Addr<11>          17: CPUAccessStrobe   31: D<6>.PIN
      4: Addr<12>          18: HorizClk          32: D<7>.PIN
      5: Addr<13>          19: HorizCount<0>     33: D<8>.PIN
      6: Addr<14>          20: D<11>.PIN         34: D<9>.PIN
      7: Addr<1>           21: D<12>.PIN         35: D<10>.PIN
      8: Addr<2>           22: D<13>.PIN         36: ReloadAccess
      9: Addr<3>           23: D<14>.PIN         37: VertCount<8>
     10: Addr<4>           24: D<15>.PIN         38: VertState_FFd1
     11: Addr<5>           25: D<0>.PIN          39: VertState_FFd2
     12: Addr<6>           26: D<1>.PIN          40: nOE
     13: Addr<7>           27: D<2>.PIN          41: nRst
     14: Addr<8>           28: D<3>.PIN          42: nWE

    Signal                        1         2         3         4         5 FB
    Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
    Addr<12>             .XXXXXXXXXXXXXX..XX................XXXX........... 20
    Addr<11>             .XXXXXXXXXXXXXX..XX................XXXX........... 20
    RamD<7>              X..............X.......X.......X.........X........ 5
    Addr<9>              ......XXXXXXXX...XX................X.............. 11
    Addr<1>              .................XX................X.............. 3
    RamD<6>              X..............X......X.......X..........X........ 5
    RamD<3>              X..............X...X.......X.............X........ 5
    Addr<10>             .XXXXXXXXXXXXXX..XX................XXXX........... 20
    Addr<2>              ......X..........XX................X.............. 4
    RamD<2>              X..............X..........X.......X......X........ 5
    RamD<5>              X..............X.....X.......X...........X........ 5
    nBlank               ......XXXXXX......X..................XX.X......... 10
    RamD<0>              X..............X........X.......X........X........ 5
    RamD<4>              X..............X....X.......X............X........ 5
    RamCE                .................................................. 0
    RamWE                ...............XX........................X........ 3
    RamOE                ...............XX..................X...X.......... 4
    RamD<1>              X..............X.........X.......X.......X........ 5
                        0----+----1----+----2----+----3----+----4----+----5
                                  0         0         0         0         0
    *******************************  Equations  ********************************

    ********** Mapped Logic **********

    FTCPE_Addr1: FTCPE port map (Addr_I(1),HorizCount(0),HorizClk,NOT nRst,'0');
    Addr(1) <= Addr_I(1) when Addr_OE(1) = '1' else 'Z';
    Addr_OE(1) <= ReloadAccess;

    FTCPE_Addr2: FTCPE port map (Addr_I(2),Addr_T(2),HorizClk,NOT nRst,'0');
    Addr_T(2) <= (Addr(1) AND HorizCount(0));
    Addr(2) <= Addr_I(2) when Addr_OE(2) = '1' else 'Z';
    Addr_OE(2) <= ReloadAccess;

    FTCPE_Addr3: FTCPE port map (Addr_I(3),Addr_T(3),HorizClk,NOT nRst,'0');
    Addr_T(3) <= (Addr(2) AND Addr(1) AND HorizCount(0));
    Addr(3) <= Addr_I(3) when Addr_OE(3) = '1' else 'Z';
    Addr_OE(3) <= ReloadAccess;

    FTCPE_Addr4: FTCPE port map (Addr_I(4),Addr_T(4),HorizClk,NOT nRst,'0');
    Addr_T(4) <= (Addr(2) AND Addr(3) AND Addr(1) AND HorizCount(0));
    Addr(4) <= Addr_I(4) when Addr_OE(4) = '1' else 'Z';
    Addr_OE(4) <= ReloadAccess;

    FTCPE_Addr5: FTCPE port map (Addr_I(5),Addr_T(5),HorizClk,NOT nRst,'0');
    Addr_T(5) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(1) AND
    	HorizCount(0));
    Addr(5) <= Addr_I(5) when Addr_OE(5) = '1' else 'Z';
    Addr_OE(5) <= ReloadAccess;

    FTCPE_Addr6: FTCPE port map (Addr_I(6),Addr_T(6),HorizClk,NOT nRst,'0');
    Addr_T(6) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND
    	Addr(1) AND HorizCount(0));
    Addr(6) <= Addr_I(6) when Addr_OE(6) = '1' else 'Z';
    Addr_OE(6) <= ReloadAccess;

    FTCPE_Addr7: FTCPE port map (Addr_I(7),Addr_T(7),HorizClk,NOT nRst,'0',Addr_CE(7));
    Addr_T(7) <= ((VertCount(1).EXP)
    	OR (NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND Addr(11) AND
    	NOT Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND NOT VertState_FFd2 AND
    	VertState_FFd1 AND NOT VertCount(8))
    	OR (NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND NOT Addr(11) AND
    	Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND VertState_FFd2 AND
    	NOT VertState_FFd1 AND NOT VertCount(8)));
    Addr_CE(7) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND
    	Addr(1) AND Addr(6) AND HorizCount(0));
    Addr(7) <= Addr_I(7) when Addr_OE(7) = '1' else 'Z';
    Addr_OE(7) <= ReloadAccess;

    FTCPE_Addr8: FTCPE port map (Addr_I(8),Addr(7),HorizClk,NOT nRst,'0',Addr_CE(8));
    Addr_CE(8) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND
    	Addr(1) AND Addr(6) AND HorizCount(0));
    Addr(8) <= Addr_I(8) when Addr_OE(8) = '1' else 'Z';
    Addr_OE(8) <= ReloadAccess;

    FTCPE_Addr9: FTCPE port map (Addr_I(9),Addr_T(9),HorizClk,NOT nRst,'0',Addr_CE(9));
    Addr_T(9) <= (Addr(7) AND Addr(8));
    Addr_CE(9) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND
    	Addr(1) AND Addr(6) AND HorizCount(0));
    Addr(9) <= Addr_I(9) when Addr_OE(9) = '1' else 'Z';
    Addr_OE(9) <= ReloadAccess;

    FTCPE_Addr10: FTCPE port map (Addr_I(10),Addr_T(10),HorizClk,NOT nRst,'0',Addr_CE(10));
    Addr_T(10) <= ((Addr(7) AND Addr(9) AND Addr(8))
    	OR (Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND NOT Addr(11) AND
    	NOT Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND NOT VertState_FFd2 AND
    	NOT VertState_FFd1 AND NOT VertCount(8)));
    Addr_CE(10) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND
    	Addr(1) AND Addr(6) AND HorizCount(0));
    Addr(10) <= Addr_I(10) when Addr_OE(10) = '1' else 'Z';
    Addr_OE(10) <= ReloadAccess;

    FTCPE_Addr11: FTCPE port map (Addr_I(11),Addr_T(11),HorizClk,NOT nRst,'0',Addr_CE(11));
    Addr_T(11) <= ((Addr(10) AND Addr(7) AND Addr(9) AND Addr(8))
    	OR (NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND Addr(11) AND
    	NOT Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND NOT VertState_FFd2 AND
    	VertState_FFd1 AND NOT VertCount(8)));
    Addr_CE(11) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND
    	Addr(1) AND Addr(6) AND HorizCount(0));
    Addr(11) <= Addr_I(11) when Addr_OE(11) = '1' else 'Z';
    Addr_OE(11) <= ReloadAccess;

    FTCPE_Addr12: FTCPE port map (Addr_I(12),Addr_T(12),HorizClk,NOT nRst,'0',Addr_CE(12));
    Addr_T(12) <= ((Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND
    	Addr(8))
    	OR (NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND NOT Addr(11) AND
    	Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND VertState_FFd2 AND
    	NOT VertState_FFd1 AND NOT VertCount(8)));
    Addr_CE(12) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND
    	Addr(1) AND Addr(6) AND HorizCount(0));
    Addr(12) <= Addr_I(12) when Addr_OE(12) = '1' else 'Z';
    Addr_OE(12) <= ReloadAccess;

    FTCPE_Addr13: FTCPE port map (Addr_I(13),Addr_T(13),HorizClk,NOT nRst,'0',Addr_CE(13));
    Addr_T(13) <= (Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND
    	Addr(12) AND Addr(8));
    Addr_CE(13) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND
    	Addr(1) AND Addr(6) AND HorizCount(0));
    Addr(13) <= Addr_I(13) when Addr_OE(13) = '1' else 'Z';
    Addr_OE(13) <= ReloadAccess;

    FTCPE_Addr14: FTCPE port map (Addr_I(14),Addr_T(14),HorizClk,NOT nRst,'0',Addr_CE(14));
    Addr_T(14) <= (Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND
    	Addr(12) AND Addr(8) AND Addr(13));
    Addr_CE(14) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND
    	Addr(1) AND Addr(6) AND HorizCount(0));
    Addr(14) <= Addr_I(14) when Addr_OE(14) = '1' else 'Z';
    Addr_OE(14) <= ReloadAccess;

    BufEn_I <= '0';
    BufEn <= BufEn_I when BufEn_OE = '1' else 'Z';
    BufEn_OE <= (CPUAccessOn AND CPUAccess);

    FTCPE_CPUAccess: FTCPE port map (CPUAccess,CPUAccess_T,ShiftClk_int,NOT nRst,'0');
    CPUAccess_T <= ((pix_count(0) AND NOT pix_count(1) AND pix_count(2) AND
    	CPUAccess)
    	OR (pix_count(0) AND NOT pix_count(1) AND NOT pix_count(2) AND
    	NOT CPUAccess));

    FDCPE_CPUAccessOn: FDCPE port map (CPUAccessOn,'1',CPUAccess,NOT CPUAccessOn/CPUAccessOn_RSTF__$INT,'0',NOT CPUAccessOn);

    CPUAccessOn/CPUAccessOn_RSTF__$INT <= (nRst AND NOT nCS);

    FTCPE_CPUAccessStrobe: FTCPE port map (CPUAccessStrobe,CPUAccessStrobe_T,ShiftClk_int,NOT nRst,'0');
    CPUAccessStrobe_T <= ((NOT pix_count(0) AND pix_count(1) AND NOT pix_count(2) AND
    	NOT CPUAccessStrobe)
    	OR (NOT pix_count(0) AND NOT pix_count(1) AND pix_count(2) AND
    	CPUAccessStrobe));

    D_I(0) <= RamD(0).PIN;
    D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
    D_OE(0) <= (CPUAccessOn AND NOT A0 AND NOT nOE);

    D_I(1) <= RamD(1).PIN;
    D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
    D_OE(1) <= (CPUAccessOn AND NOT A0 AND NOT nOE);

    D_I(2) <= RamD(2).PIN;
    D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
    D_OE(2) <= (CPUAccessOn AND NOT A0 AND NOT nOE);

    D_I(3) <= RamD(3).PIN;
    D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
    D_OE(3) <= (CPUAccessOn AND NOT A0 AND NOT nOE);

    D_I(4) <= RamD(4).PIN;
    D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
    D_OE(4) <= (CPUAccessOn AND NOT A0 AND NOT nOE);

    D_I(5) <= RamD(5).PIN;
    D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
    D_OE(5) <= (CPUAccessOn AND NOT A0 AND NOT nOE);

    D_I(6) <= RamD(6).PIN;
    D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
    D_OE(6) <= (CPUAccessOn AND NOT A0 AND NOT nOE);

    D_I(7) <= RamD(7).PIN;
    D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
    D_OE(7) <= (CPUAccessOn AND NOT A0 AND NOT nOE);

    D_I(8) <= RamD(0).PIN;
    D(8) <= D_I(8) when D_OE(8) = '1' else 'Z';
    D_OE(8) <= (CPUAccessOn AND A0 AND NOT nOE);

    D_I(9) <= RamD(1).PIN;
    D(9) <= D_I(9) when D_OE(9) = '1' else 'Z';
    D_OE(9) <= (CPUAccessOn AND A0 AND NOT nOE);

    D_I(10) <= RamD(2).PIN;
    D(10) <= D_I(10) when D_OE(10) = '1' else 'Z';
    D_OE(10) <= (CPUAccessOn AND A0 AND NOT nOE);

    D_I(11) <= RamD(3).PIN;
    D(11) <= D_I(11) when D_OE(11) = '1' else 'Z';
    D_OE(11) <= (CPUAccessOn AND A0 AND NOT nOE);

    D_I(12) <= RamD(4).PIN;
    D(12) <= D_I(12) when D_OE(12) = '1' else 'Z';
    D_OE(12) <= (CPUAccessOn AND A0 AND NOT nOE);

    D_I(13) <= RamD(5).PIN;
    D(13) <= D_I(13) when D_OE(13) = '1' else 'Z';
    D_OE(13) <= (CPUAccessOn AND A0 AND NOT nOE);

    D_I(14) <= RamD(6).PIN;
    D(14) <= D_I(14) when D_OE(14) = '1' else 'Z';
    D_OE(14) <= (CPUAccessOn AND A0 AND NOT nOE);

    D_I(15) <= RamD(7).PIN;
    D(15) <= D_I(15) when D_OE(15) = '1' else 'Z';
    D_OE(15) <= (CPUAccessOn AND A0 AND NOT nOE);

    FTCPE_HorizClk: FTCPE port map (HorizClk,HorizClk_T,ShiftClk_int,'0','0',nRst);
    HorizClk_T <= ((HorizClk AND pix_count(0) AND NOT pix_count(1) AND
    	NOT pix_count(2))
    	OR (NOT HorizClk AND NOT pix_count(0) AND NOT pix_count(1) AND
    	NOT pix_count(2)));

    FTCPE_HorizCount0: FTCPE port map (HorizCount(0),'1',HorizClk,NOT nRst,'0');

    FDCPE_IntWait: FDCPE port map (IntWait,'1',NOT nCS,IntWait/IntWait_RSTF,'0');

    IntWait/IntWait_RSTF <= pix_count(1).EXP;

    RamCE <= '0';

    RamD_I(0) <= ((RamD_4_IOBUFE.EXP)
    	OR (nWE AND D(8).PIN));
    RamD(0) <= RamD_I(0) when RamD_OE(0) = '1' else 'Z';
    RamD_OE(0) <= (CPUAccessOn AND NOT nWE);

    RamD_I(1) <= ((NOT CPUAccessOn AND D(9).PIN)
    	OR (A0 AND D(9).PIN)
    	OR (nWE AND D(9).PIN)
    	OR (CPUAccessOn AND NOT A0 AND NOT nWE AND D(1).PIN));
    RamD(1) <= RamD_I(1) when RamD_OE(1) = '1' else 'Z';
    RamD_OE(1) <= (CPUAccessOn AND NOT nWE);

    RamD_I(2) <= ((NOT CPUAccessOn AND D(10).PIN)
    	OR (A0 AND D(10).PIN)
    	OR (nWE AND D(10).PIN)
    	OR (CPUAccessOn AND NOT A0 AND NOT nWE AND D(2).PIN));
    RamD(2) <= RamD_I(2) when RamD_OE(2) = '1' else 'Z';
    RamD_OE(2) <= (CPUAccessOn AND NOT nWE);

    RamD_I(3) <= ((NOT CPUAccessOn AND D(11).PIN)
    	OR (A0 AND D(11).PIN)
    	OR (nWE AND D(11).PIN)
    	OR (CPUAccessOn AND NOT A0 AND NOT nWE AND D(3).PIN));
    RamD(3) <= RamD_I(3) when RamD_OE(3) = '1' else 'Z';
    RamD_OE(3) <= (CPUAccessOn AND NOT nWE);

    RamD_I(4) <= ((RamCE_OBUF.EXP)
    	OR (nWE AND D(12).PIN));
    RamD(4) <= RamD_I(4) when RamD_OE(4) = '1' else 'Z';
    RamD_OE(4) <= (CPUAccessOn AND NOT nWE);

    RamD_I(5) <= ((NOT CPUAccessOn AND D(13).PIN)
    	OR (A0 AND D(13).PIN)
    	OR (nWE AND D(13).PIN)
    	OR (CPUAccessOn AND NOT A0 AND NOT nWE AND D(5).PIN));
    RamD(5) <= RamD_I(5) when RamD_OE(5) = '1' else 'Z';
    RamD_OE(5) <= (CPUAccessOn AND NOT nWE);

    RamD_I(6) <= ((NOT CPUAccessOn AND D(14).PIN)
    	OR (A0 AND D(14).PIN)
    	OR (nWE AND D(14).PIN)
    	OR (CPUAccessOn AND NOT A0 AND NOT nWE AND D(6).PIN));
    RamD(6) <= RamD_I(6) when RamD_OE(6) = '1' else 'Z';
    RamD_OE(6) <= (CPUAccessOn AND NOT nWE);

    RamD_I(7) <= ((NOT CPUAccessOn AND D(15).PIN)
    	OR (A0 AND D(15).PIN)
    	OR (nWE AND D(15).PIN)
    	OR (CPUAccessOn AND NOT A0 AND NOT nWE AND D(7).PIN));
    RamD(7) <= RamD_I(7) when RamD_OE(7) = '1' else 'Z';
    RamD_OE(7) <= (CPUAccessOn AND NOT nWE);

    RamOE <= NOT (((ReloadAccess)
    	OR (CPUAccessOn AND CPUAccessStrobe AND NOT nOE)));

    RamWE <= NOT ((CPUAccessOn AND CPUAccessStrobe AND NOT nWE));

    FDCPE_ReloadAccess: FDCPE port map (ReloadAccess,ReloadAccess_D,ShiftClk_int,NOT nRst,'0');
    ReloadAccess_D <= ((D_10_IOBUFE$BUF1.EXP)
    	OR (HorizClk.EXP)
    	OR (NOT VertState_FFd2 AND NOT ReloadAccess)
    	OR (NOT VertState_FFd1 AND NOT ReloadAccess)
    	OR (NOT ReloadAccess AND NOT pix_count(1))
    	OR (NOT ReloadAccess AND NOT pix_count(2)));

    FDCPE_ReloadReady: FDCPE port map (ReloadReady,ReloadReady_D,ShiftClk_int,'0','0',nRst);
    ReloadReady_D <= ((D_4_IOBUFE$BUF1.EXP)
    	OR (D_5_IOBUFE$BUF1.EXP)
    	OR (NOT VertState_FFd2 AND NOT ReloadReady)
    	OR (NOT VertState_FFd1 AND NOT ReloadReady)
    	OR (NOT pix_count(1) AND NOT ReloadReady));

    SA0_I <= ((ReloadAccess AND HorizCount(0))
    	OR (NOT ReloadAccess AND A0));
    SA0 <= SA0_I when SA0_OE = '1' else 'Z';
    SA0_OE <= NOT ((NOT ReloadAccess AND NOT CPUAccessOn));

    ShiftClk <= NOT ((VertState_FFd2 AND VertState_FFd1 AND NOT ShiftClk_int AND
    	NOT ReloadReady));

    FTCPE_ShiftClk_int: FTCPE port map (ShiftClk_int,'1',NOT Clk,NOT nRst,'0');

    FDCPE_ShiftLoad: FDCPE port map (ShiftLoad,'0',NOT Clk,NOT nRst,NOT ReloadReady);

    FTCPE_VertCount8: FTCPE port map (VertCount(8),VertCount_T(8),HorizClk,NOT nRst,'0',VertCount_CE(8));
    VertCount_T(8) <= ((Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND
    	Addr(12) AND Addr(8) AND Addr(13) AND Addr(14) AND NOT VertState_FFd2)
    	OR (Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND
    	Addr(12) AND Addr(8) AND Addr(13) AND Addr(14) AND NOT VertState_FFd1)
    	OR (Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND
    	Addr(12) AND Addr(8) AND Addr(13) AND Addr(14) AND VertCount(8)));
    VertCount_CE(8) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND
    	Addr(1) AND Addr(6) AND HorizCount(0));

    FTCPE_VertState_FFd1: FTCPE port map (VertState_FFd1,VertState_FFd1_T,HorizClk,NOT nRst,'0',VertState_FFd1_CE);
    VertState_FFd1_T <= ((NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND Addr(11) AND
    	NOT Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND NOT VertState_FFd2 AND
    	VertState_FFd1 AND NOT VertCount(8))
    	OR (NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND NOT Addr(11) AND
    	Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND VertState_FFd2 AND
    	NOT VertState_FFd1 AND NOT VertCount(8)));
    VertState_FFd1_CE <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND
    	Addr(1) AND Addr(6) AND HorizCount(0));

    FTCPE_VertState_FFd2: FTCPE port map (VertState_FFd2,VertState_FFd2_T,HorizClk,NOT nRst,'0',VertState_FFd2_CE);
    VertState_FFd2_T <= ((Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND
    	Addr(12) AND Addr(8) AND Addr(13) AND Addr(14) AND VertState_FFd2 AND
    	VertState_FFd1 AND NOT VertCount(8))
    	OR (Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND NOT Addr(11) AND
    	NOT Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND NOT VertState_FFd2 AND
    	NOT VertState_FFd1 AND NOT VertCount(8)));
    VertState_FFd2_CE <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND
    	Addr(1) AND Addr(6) AND HorizCount(0));

    nBlank <= NOT (((NOT nRst)
    	OR (NOT VertState_FFd2)
    	OR (NOT VertState_FFd1)
    	OR (RamD_0_IOBUFE.EXP)
    	OR (NOT Addr(4) AND NOT Addr(5) AND NOT Addr(6))
    	OR (NOT Addr(2) AND NOT Addr(3) AND NOT Addr(5) AND NOT Addr(6))));

    nSync <= nSync_BUFR;

    nSync_BUFR <= NOT (((EXP7_.EXP)
    	OR (EXP8_.EXP)
    	OR (nRst AND NOT Addr(2) AND NOT Addr(4) AND NOT Addr(5) AND NOT Addr(1) AND
    	NOT Addr(6) AND VertState_FFd2 AND NOT HorizCount(0))
    	OR (nRst AND NOT Addr(2) AND NOT Addr(4) AND NOT Addr(5) AND NOT Addr(1) AND
    	NOT Addr(6) AND VertState_FFd1 AND NOT HorizCount(0))
    	OR (nRst AND NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND Addr(8) AND
    	NOT Addr(3) AND Addr(6) AND NOT VertState_FFd2 AND NOT VertState_FFd1)
    	OR (nRst AND NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND Addr(8) AND
    	NOT Addr(5) AND Addr(6) AND NOT VertState_FFd2 AND NOT VertState_FFd1)
    	OR (nRst AND NOT Addr(10) AND NOT Addr(9) AND Addr(8) AND NOT Addr(4) AND
    	Addr(5) AND Addr(6) AND NOT VertState_FFd2 AND NOT VertState_FFd1)));

    FTCPE_pix_count0: FTCPE port map (pix_count(0),'1',ShiftClk_int,NOT nRst,'0');

    FTCPE_pix_count1: FTCPE port map (pix_count(1),pix_count(0),ShiftClk_int,NOT nRst,'0');

    FTCPE_pix_count2: FTCPE port map (pix_count(2),pix_count_T(2),ShiftClk_int,NOT nRst,'0');
    pix_count_T(2) <= (pix_count(0) AND pix_count(1));

    xWait <= ((NOT nWait_in)
    	OR (NOT nCS AND IntWait));

    Register Legend:
     FDCPE (Q,D,C,CLR,PRE,CE);
     FTCPE (Q,D,C,CLR,PRE,CE);
     LDCP  (Q,D,G,CLR,PRE);

    ******************************  Device Pin Out *****************************

    Device : XC9572XL-7-TQ100

       --------------------------------------------------
      /100 98  96  94  92  90  88  86  84  82  80  78  76  \
     |   99  97  95  93  91  89  87  85  83  81  79  77    |
     | 1                                               75  |
     | 2                                               74  |
     | 3                                               73  |
     | 4                                               72  |
     | 5                                               71  |
     | 6                                               70  |
     | 7                                               69  |
     | 8                                               68  |
     | 9                                               67  |
     | 10                                              66  |
     | 11                                              65  |
     | 12                                              64  |
     | 13               XC9572XL-7-TQ100               63  |
     | 14                                              62  |
     | 15                                              61  |
     | 16                                              60  |
     | 17                                              59  |
     | 18                                              58  |
     | 19                                              57  |
     | 20                                              56  |
     | 21                                              55  |
     | 22                                              54  |
     | 23                                              53  |
     | 24                                              52  |
     | 25                                              51  |
     |   27  29  31  33  35  37  39  41  43  45  47  49    |
      \26  28  30  32  34  36  38  40  42  44  46  48  50  /
       --------------------------------------------------

    Pin Signal                         Pin Signal
    No. Name                           No. Name
      1 KPR                              51 VCC
      2 NC                               52 KPR
      3 KPR                              53 KPR
      4 KPR                              54 SA0
      5 VCC                              55 Addr<8>
      6 KPR                              56 Addr<7>
      7 NC                               57 VCC
      8 Clk                              58 Addr<6>
      9 KPR                              59 Addr<14>
     10 KPR                              60 Addr<5>
     11 D<7>                             61 Addr<4>
     12 D<6>                             62 GND
     13 D<5>                             63 Addr<13>
     14 D<4>                             64 Addr<3>
     15 D<3>                             65 Addr<12>
     16 D<2>                             66 Addr<2>
     17 D<1>                             67 Addr<11>
     18 D<0>                             68 Addr<1>
     19 NC                               69 GND
     20 nWait_in                         70 Addr<10>
     21 GND                              71 RamD<7>
     22 nWE                              72 Addr<9>
     23 nOE                              73 NC
     24 NC                               74 RamD<5>
     25 xWait                            75 GND
     26 VCC                              76 RamD<6>
     27 KPR                              77 RamD<3>
     28 BufEn                            78 RamD<4>
     29 nCS                              79 RamD<1>
     30 KPR                              80 NC
     31 GND                              81 RamD<2>
     32 KPR                              82 nBlank
     33 D<8>                             83 TDO
     34 NC                               84 GND
     35 D<9>                             85 RamD<0>
     36 D<10>                            86 RamWE
     37 D<11>                            87 nSync
     38 VCC                              88 VCC
     39 D<12>                            89 RamCE
     40 D<13>                            90 RamOE
     41 D<14>                            91 ShiftClk
     42 D<15>                            92 ShiftLoad
     43 NC                               93 KPR
     44 GND                              94 KPR
     45 TDI                              95 KPR
     46 NC                               96 KPR
     47 TMS                              97 KPR
     48 TCK                              98 VCC
     49 A0                               99 nRst
     50 KPR                             100 GND

    Legend :  NC  = Not Connected, unbonded pin
             PGND = Unused I/O configured as additional Ground pin
             TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
             KPR  = Unused I/O with weak keeper (leave unconnected)
             VCC  = Dedicated Power Pin
             GND  = Dedicated Ground Pin
             TDI  = Test Data In, JTAG pin
             TDO  = Test Data Out, JTAG pin
             TCK  = Test Clock, JTAG pin
             TMS  = Test Mode Select, JTAG pin
      PROHIBITED  = User reserved pin
    ****************************  Compiler Options  ****************************

    Following is a list of all global compiler options used by the fitter run.

    Device(s) Specified                         : xc9572xl-7-TQ100
    Optimization Method                         : SPEED
    Multi-Level Logic Optimization              : ON
    Ignore Timing Specifications                : OFF
    Default Register Power Up Value             : LOW
    Keep User Location Constraints              : ON
    What-You-See-Is-What-You-Get                : OFF
    Exhaustive Fitting                          : OFF
    Keep Unused Inputs                          : OFF
    Slew Rate                                   : FAST
    Power Mode                                  : STD
    Ground on Unused IOs                        : OFF
    Set I/O Pin Termination                     : KEEPER
    Global Clock Optimization                   : ON
    Global Set/Reset Optimization               : ON
    Global Ouput Enable Optimization            : ON
    Input Limit                                 : 54
    Pterm Limit                                 : 50