### Equations

********** Mapped Logic **********
FTCPE_Addr1: FTCPE port map (Addr_I(1),HorizCount(0),HorizClk,NOT nRst,'0'); Addr(1) <= Addr_I(1) when Addr_OE(1) = '1' else 'Z'; Addr_OE(1) <= ReloadAccess;
FTCPE_Addr2: FTCPE port map (Addr_I(2),Addr_T(2),HorizClk,NOT nRst,'0'); Addr_T(2) <= (Addr(1) AND HorizCount(0)); Addr(2) <= Addr_I(2) when Addr_OE(2) = '1' else 'Z'; Addr_OE(2) <= ReloadAccess;
FTCPE_Addr3: FTCPE port map (Addr_I(3),Addr_T(3),HorizClk,NOT nRst,'0'); Addr_T(3) <= (Addr(2) AND Addr(1) AND HorizCount(0)); Addr(3) <= Addr_I(3) when Addr_OE(3) = '1' else 'Z'; Addr_OE(3) <= ReloadAccess;
FTCPE_Addr4: FTCPE port map (Addr_I(4),Addr_T(4),HorizClk,NOT nRst,'0'); Addr_T(4) <= (Addr(2) AND Addr(3) AND Addr(1) AND HorizCount(0)); Addr(4) <= Addr_I(4) when Addr_OE(4) = '1' else 'Z'; Addr_OE(4) <= ReloadAccess;
FTCPE_Addr5: FTCPE port map (Addr_I(5),Addr_T(5),HorizClk,NOT nRst,'0'); Addr_T(5) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(1) AND HorizCount(0)); Addr(5) <= Addr_I(5) when Addr_OE(5) = '1' else 'Z'; Addr_OE(5) <= ReloadAccess;
FTCPE_Addr6: FTCPE port map (Addr_I(6),Addr_T(6),HorizClk,NOT nRst,'0'); Addr_T(6) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND Addr(1) AND HorizCount(0)); Addr(6) <= Addr_I(6) when Addr_OE(6) = '1' else 'Z'; Addr_OE(6) <= ReloadAccess;
FTCPE_Addr7: FTCPE port map (Addr_I(7),Addr_T(7),HorizClk,NOT nRst,'0',Addr_CE(7)); Addr_T(7) <= ((VertCount(1).EXP) OR (NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND Addr(11) AND NOT Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND NOT VertState_FFd2 AND VertState_FFd1 AND NOT VertCount(8)) OR (NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND NOT Addr(11) AND Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND VertState_FFd2 AND NOT VertState_FFd1 AND NOT VertCount(8))); Addr_CE(7) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND Addr(1) AND Addr(6) AND HorizCount(0)); Addr(7) <= Addr_I(7) when Addr_OE(7) = '1' else 'Z'; Addr_OE(7) <= ReloadAccess;
FTCPE_Addr8: FTCPE port map (Addr_I(8),Addr(7),HorizClk,NOT nRst,'0',Addr_CE(8)); Addr_CE(8) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND Addr(1) AND Addr(6) AND HorizCount(0)); Addr(8) <= Addr_I(8) when Addr_OE(8) = '1' else 'Z'; Addr_OE(8) <= ReloadAccess;
FTCPE_Addr9: FTCPE port map (Addr_I(9),Addr_T(9),HorizClk,NOT nRst,'0',Addr_CE(9)); Addr_T(9) <= (Addr(7) AND Addr(8)); Addr_CE(9) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND Addr(1) AND Addr(6) AND HorizCount(0)); Addr(9) <= Addr_I(9) when Addr_OE(9) = '1' else 'Z'; Addr_OE(9) <= ReloadAccess;
FTCPE_Addr10: FTCPE port map (Addr_I(10),Addr_T(10),HorizClk,NOT nRst,'0',Addr_CE(10)); Addr_T(10) <= ((Addr(7) AND Addr(9) AND Addr(8)) OR (Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND NOT Addr(11) AND NOT Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND NOT VertState_FFd2 AND NOT VertState_FFd1 AND NOT VertCount(8))); Addr_CE(10) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND Addr(1) AND Addr(6) AND HorizCount(0)); Addr(10) <= Addr_I(10) when Addr_OE(10) = '1' else 'Z'; Addr_OE(10) <= ReloadAccess;
FTCPE_Addr11: FTCPE port map (Addr_I(11),Addr_T(11),HorizClk,NOT nRst,'0',Addr_CE(11)); Addr_T(11) <= ((Addr(10) AND Addr(7) AND Addr(9) AND Addr(8)) OR (NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND Addr(11) AND NOT Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND NOT VertState_FFd2 AND VertState_FFd1 AND NOT VertCount(8))); Addr_CE(11) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND Addr(1) AND Addr(6) AND HorizCount(0)); Addr(11) <= Addr_I(11) when Addr_OE(11) = '1' else 'Z'; Addr_OE(11) <= ReloadAccess;
FTCPE_Addr12: FTCPE port map (Addr_I(12),Addr_T(12),HorizClk,NOT nRst,'0',Addr_CE(12)); Addr_T(12) <= ((Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND Addr(8)) OR (NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND NOT Addr(11) AND Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND VertState_FFd2 AND NOT VertState_FFd1 AND NOT VertCount(8))); Addr_CE(12) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND Addr(1) AND Addr(6) AND HorizCount(0)); Addr(12) <= Addr_I(12) when Addr_OE(12) = '1' else 'Z'; Addr_OE(12) <= ReloadAccess;
FTCPE_Addr13: FTCPE port map (Addr_I(13),Addr_T(13),HorizClk,NOT nRst,'0',Addr_CE(13)); Addr_T(13) <= (Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND Addr(12) AND Addr(8)); Addr_CE(13) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND Addr(1) AND Addr(6) AND HorizCount(0)); Addr(13) <= Addr_I(13) when Addr_OE(13) = '1' else 'Z'; Addr_OE(13) <= ReloadAccess;
FTCPE_Addr14: FTCPE port map (Addr_I(14),Addr_T(14),HorizClk,NOT nRst,'0',Addr_CE(14)); Addr_T(14) <= (Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND Addr(12) AND Addr(8) AND Addr(13)); Addr_CE(14) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND Addr(1) AND Addr(6) AND HorizCount(0)); Addr(14) <= Addr_I(14) when Addr_OE(14) = '1' else 'Z'; Addr_OE(14) <= ReloadAccess;
BufEn_I <= '0'; BufEn <= BufEn_I when BufEn_OE = '1' else 'Z'; BufEn_OE <= (CPUAccessOn AND CPUAccess);
FTCPE_CPUAccess: FTCPE port map (CPUAccess,CPUAccess_T,ShiftClk_int,NOT nRst,'0'); CPUAccess_T <= ((pix_count(0) AND NOT pix_count(1) AND pix_count(2) AND CPUAccess) OR (pix_count(0) AND NOT pix_count(1) AND NOT pix_count(2) AND NOT CPUAccess));
FDCPE_CPUAccessOn: FDCPE port map (CPUAccessOn,'1',CPUAccess,NOT CPUAccessOn/CPUAccessOn_RSTF__$INT,'0',NOT CPUAccessOn);
CPUAccessOn/CPUAccessOn_RSTF__$INT <= (nRst AND NOT nCS);
FTCPE_CPUAccessStrobe: FTCPE port map (CPUAccessStrobe,CPUAccessStrobe_T,ShiftClk_int,NOT nRst,'0'); CPUAccessStrobe_T <= ((NOT pix_count(0) AND pix_count(1) AND NOT pix_count(2) AND NOT CPUAccessStrobe) OR (NOT pix_count(0) AND NOT pix_count(1) AND pix_count(2) AND CPUAccessStrobe));
D_I(0) <= RamD(0).PIN; D(0) <= D_I(0) when D_OE(0) = '1' else 'Z'; D_OE(0) <= (CPUAccessOn AND NOT A0 AND NOT nOE);
D_I(1) <= RamD(1).PIN; D(1) <= D_I(1) when D_OE(1) = '1' else 'Z'; D_OE(1) <= (CPUAccessOn AND NOT A0 AND NOT nOE);
D_I(2) <= RamD(2).PIN; D(2) <= D_I(2) when D_OE(2) = '1' else 'Z'; D_OE(2) <= (CPUAccessOn AND NOT A0 AND NOT nOE);
D_I(3) <= RamD(3).PIN; D(3) <= D_I(3) when D_OE(3) = '1' else 'Z'; D_OE(3) <= (CPUAccessOn AND NOT A0 AND NOT nOE);
D_I(4) <= RamD(4).PIN; D(4) <= D_I(4) when D_OE(4) = '1' else 'Z'; D_OE(4) <= (CPUAccessOn AND NOT A0 AND NOT nOE);
D_I(5) <= RamD(5).PIN; D(5) <= D_I(5) when D_OE(5) = '1' else 'Z'; D_OE(5) <= (CPUAccessOn AND NOT A0 AND NOT nOE);
D_I(6) <= RamD(6).PIN; D(6) <= D_I(6) when D_OE(6) = '1' else 'Z'; D_OE(6) <= (CPUAccessOn AND NOT A0 AND NOT nOE);
D_I(7) <= RamD(7).PIN; D(7) <= D_I(7) when D_OE(7) = '1' else 'Z'; D_OE(7) <= (CPUAccessOn AND NOT A0 AND NOT nOE);
D_I(8) <= RamD(0).PIN; D(8) <= D_I(8) when D_OE(8) = '1' else 'Z'; D_OE(8) <= (CPUAccessOn AND A0 AND NOT nOE);
D_I(9) <= RamD(1).PIN; D(9) <= D_I(9) when D_OE(9) = '1' else 'Z'; D_OE(9) <= (CPUAccessOn AND A0 AND NOT nOE);
D_I(10) <= RamD(2).PIN; D(10) <= D_I(10) when D_OE(10) = '1' else 'Z'; D_OE(10) <= (CPUAccessOn AND A0 AND NOT nOE);
D_I(11) <= RamD(3).PIN; D(11) <= D_I(11) when D_OE(11) = '1' else 'Z'; D_OE(11) <= (CPUAccessOn AND A0 AND NOT nOE);
D_I(12) <= RamD(4).PIN; D(12) <= D_I(12) when D_OE(12) = '1' else 'Z'; D_OE(12) <= (CPUAccessOn AND A0 AND NOT nOE);
D_I(13) <= RamD(5).PIN; D(13) <= D_I(13) when D_OE(13) = '1' else 'Z'; D_OE(13) <= (CPUAccessOn AND A0 AND NOT nOE);
D_I(14) <= RamD(6).PIN; D(14) <= D_I(14) when D_OE(14) = '1' else 'Z'; D_OE(14) <= (CPUAccessOn AND A0 AND NOT nOE);
D_I(15) <= RamD(7).PIN; D(15) <= D_I(15) when D_OE(15) = '1' else 'Z'; D_OE(15) <= (CPUAccessOn AND A0 AND NOT nOE);
FTCPE_HorizClk: FTCPE port map (HorizClk,HorizClk_T,ShiftClk_int,'0','0',nRst); HorizClk_T <= ((HorizClk AND pix_count(0) AND NOT pix_count(1) AND NOT pix_count(2)) OR (NOT HorizClk AND NOT pix_count(0) AND NOT pix_count(1) AND NOT pix_count(2)));
FTCPE_HorizCount0: FTCPE port map (HorizCount(0),'1',HorizClk,NOT nRst,'0');
FDCPE_IntWait: FDCPE port map (IntWait,'1',NOT nCS,IntWait/IntWait_RSTF,'0');
IntWait/IntWait_RSTF <= pix_count(1).EXP;
RamCE <= '0';
RamD_I(0) <= ((RamD_4_IOBUFE.EXP) OR (nWE AND D(8).PIN)); RamD(0) <= RamD_I(0) when RamD_OE(0) = '1' else 'Z'; RamD_OE(0) <= (CPUAccessOn AND NOT nWE);
RamD_I(1) <= ((NOT CPUAccessOn AND D(9).PIN) OR (A0 AND D(9).PIN) OR (nWE AND D(9).PIN) OR (CPUAccessOn AND NOT A0 AND NOT nWE AND D(1).PIN)); RamD(1) <= RamD_I(1) when RamD_OE(1) = '1' else 'Z'; RamD_OE(1) <= (CPUAccessOn AND NOT nWE);
RamD_I(2) <= ((NOT CPUAccessOn AND D(10).PIN) OR (A0 AND D(10).PIN) OR (nWE AND D(10).PIN) OR (CPUAccessOn AND NOT A0 AND NOT nWE AND D(2).PIN)); RamD(2) <= RamD_I(2) when RamD_OE(2) = '1' else 'Z'; RamD_OE(2) <= (CPUAccessOn AND NOT nWE);
RamD_I(3) <= ((NOT CPUAccessOn AND D(11).PIN) OR (A0 AND D(11).PIN) OR (nWE AND D(11).PIN) OR (CPUAccessOn AND NOT A0 AND NOT nWE AND D(3).PIN)); RamD(3) <= RamD_I(3) when RamD_OE(3) = '1' else 'Z'; RamD_OE(3) <= (CPUAccessOn AND NOT nWE);
RamD_I(4) <= ((RamCE_OBUF.EXP) OR (nWE AND D(12).PIN)); RamD(4) <= RamD_I(4) when RamD_OE(4) = '1' else 'Z'; RamD_OE(4) <= (CPUAccessOn AND NOT nWE);
RamD_I(5) <= ((NOT CPUAccessOn AND D(13).PIN) OR (A0 AND D(13).PIN) OR (nWE AND D(13).PIN) OR (CPUAccessOn AND NOT A0 AND NOT nWE AND D(5).PIN)); RamD(5) <= RamD_I(5) when RamD_OE(5) = '1' else 'Z'; RamD_OE(5) <= (CPUAccessOn AND NOT nWE);
RamD_I(6) <= ((NOT CPUAccessOn AND D(14).PIN) OR (A0 AND D(14).PIN) OR (nWE AND D(14).PIN) OR (CPUAccessOn AND NOT A0 AND NOT nWE AND D(6).PIN)); RamD(6) <= RamD_I(6) when RamD_OE(6) = '1' else 'Z'; RamD_OE(6) <= (CPUAccessOn AND NOT nWE);
RamD_I(7) <= ((NOT CPUAccessOn AND D(15).PIN) OR (A0 AND D(15).PIN) OR (nWE AND D(15).PIN) OR (CPUAccessOn AND NOT A0 AND NOT nWE AND D(7).PIN)); RamD(7) <= RamD_I(7) when RamD_OE(7) = '1' else 'Z'; RamD_OE(7) <= (CPUAccessOn AND NOT nWE);
RamOE <= NOT (((ReloadAccess) OR (CPUAccessOn AND CPUAccessStrobe AND NOT nOE)));
RamWE <= NOT ((CPUAccessOn AND CPUAccessStrobe AND NOT nWE));
FDCPE_ReloadAccess: FDCPE port map (ReloadAccess,ReloadAccess_D,ShiftClk_int,NOT nRst,'0'); ReloadAccess_D <= ((D_10_IOBUFE$BUF1.EXP) OR (HorizClk.EXP) OR (NOT VertState_FFd2 AND NOT ReloadAccess) OR (NOT VertState_FFd1 AND NOT ReloadAccess) OR (NOT ReloadAccess AND NOT pix_count(1)) OR (NOT ReloadAccess AND NOT pix_count(2)));
FDCPE_ReloadReady: FDCPE port map (ReloadReady,ReloadReady_D,ShiftClk_int,'0','0',nRst); ReloadReady_D <= ((D_4_IOBUFE$BUF1.EXP) OR (D_5_IOBUFE$BUF1.EXP) OR (NOT VertState_FFd2 AND NOT ReloadReady) OR (NOT VertState_FFd1 AND NOT ReloadReady) OR (NOT pix_count(1) AND NOT ReloadReady));
SA0_I <= ((ReloadAccess AND HorizCount(0)) OR (NOT ReloadAccess AND A0)); SA0 <= SA0_I when SA0_OE = '1' else 'Z'; SA0_OE <= NOT ((NOT ReloadAccess AND NOT CPUAccessOn));
ShiftClk <= NOT ((VertState_FFd2 AND VertState_FFd1 AND NOT ShiftClk_int AND NOT ReloadReady));
FTCPE_ShiftClk_int: FTCPE port map (ShiftClk_int,'1',NOT Clk,NOT nRst,'0');
FDCPE_ShiftLoad: FDCPE port map (ShiftLoad,'0',NOT Clk,NOT nRst,NOT ReloadReady);
FTCPE_VertCount8: FTCPE port map (VertCount(8),VertCount_T(8),HorizClk,NOT nRst,'0',VertCount_CE(8)); VertCount_T(8) <= ((Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND Addr(12) AND Addr(8) AND Addr(13) AND Addr(14) AND NOT VertState_FFd2) OR (Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND Addr(12) AND Addr(8) AND Addr(13) AND Addr(14) AND NOT VertState_FFd1) OR (Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND Addr(12) AND Addr(8) AND Addr(13) AND Addr(14) AND VertCount(8))); VertCount_CE(8) <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND Addr(1) AND Addr(6) AND HorizCount(0));
FTCPE_VertState_FFd1: FTCPE port map (VertState_FFd1,VertState_FFd1_T,HorizClk,NOT nRst,'0',VertState_FFd1_CE); VertState_FFd1_T <= ((NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND Addr(11) AND NOT Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND NOT VertState_FFd2 AND VertState_FFd1 AND NOT VertCount(8)) OR (NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND NOT Addr(11) AND Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND VertState_FFd2 AND NOT VertState_FFd1 AND NOT VertCount(8))); VertState_FFd1_CE <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND Addr(1) AND Addr(6) AND HorizCount(0));
FTCPE_VertState_FFd2: FTCPE port map (VertState_FFd2,VertState_FFd2_T,HorizClk,NOT nRst,'0',VertState_FFd2_CE); VertState_FFd2_T <= ((Addr(10) AND Addr(7) AND Addr(9) AND Addr(11) AND Addr(12) AND Addr(8) AND Addr(13) AND Addr(14) AND VertState_FFd2 AND VertState_FFd1 AND NOT VertCount(8)) OR (Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND NOT Addr(11) AND NOT Addr(12) AND NOT Addr(8) AND NOT Addr(13) AND NOT Addr(14) AND NOT VertState_FFd2 AND NOT VertState_FFd1 AND NOT VertCount(8))); VertState_FFd2_CE <= (Addr(2) AND Addr(3) AND Addr(4) AND Addr(5) AND Addr(1) AND Addr(6) AND HorizCount(0));
nBlank <= NOT (((NOT nRst) OR (NOT VertState_FFd2) OR (NOT VertState_FFd1) OR (RamD_0_IOBUFE.EXP) OR (NOT Addr(4) AND NOT Addr(5) AND NOT Addr(6)) OR (NOT Addr(2) AND NOT Addr(3) AND NOT Addr(5) AND NOT Addr(6))));
nSync <= nSync_BUFR;
nSync_BUFR <= NOT (((EXP7_.EXP) OR (EXP8_.EXP) OR (nRst AND NOT Addr(2) AND NOT Addr(4) AND NOT Addr(5) AND NOT Addr(1) AND NOT Addr(6) AND VertState_FFd2 AND NOT HorizCount(0)) OR (nRst AND NOT Addr(2) AND NOT Addr(4) AND NOT Addr(5) AND NOT Addr(1) AND NOT Addr(6) AND VertState_FFd1 AND NOT HorizCount(0)) OR (nRst AND NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND Addr(8) AND NOT Addr(3) AND Addr(6) AND NOT VertState_FFd2 AND NOT VertState_FFd1) OR (nRst AND NOT Addr(10) AND NOT Addr(7) AND NOT Addr(9) AND Addr(8) AND NOT Addr(5) AND Addr(6) AND NOT VertState_FFd2 AND NOT VertState_FFd1) OR (nRst AND NOT Addr(10) AND NOT Addr(9) AND Addr(8) AND NOT Addr(4) AND Addr(5) AND Addr(6) AND NOT VertState_FFd2 AND NOT VertState_FFd1)));
FTCPE_pix_count0: FTCPE port map (pix_count(0),'1',ShiftClk_int,NOT nRst,'0');
FTCPE_pix_count1: FTCPE port map (pix_count(1),pix_count(0),ShiftClk_int,NOT nRst,'0');
FTCPE_pix_count2: FTCPE port map (pix_count(2),pix_count_T(2),ShiftClk_int,NOT nRst,'0'); pix_count_T(2) <= (pix_count(0) AND pix_count(1));
xWait <= ((NOT nWait_in) OR (NOT nCS AND IntWait));
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE);