AN0013 - TV video output for the EB675001DIP

Completed real AN0013 circuit boardSections:
PCB Design
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This application note describes creating a dumb framebuffer with PAL composite TV output for the EB675001DIP. The design uses a minimal number of additional components to achieve this display. The user CPLD is used to provide all control and timing logic reducing circuit complexity .

More in depth information on composite video, associated circuits and techniques can be found across the web a useful resource is the epanorama list of links and Rickard Gunée video howto


Generating composite video

Monochrome composite video can be generated with a very simple method. By using two logic outputs and carefully selected resistor values the required voltage levels can be generated.

PAL video timingsComposite video in its most basic form consists of a voltage level between 0 and 1V, where 0 V is used for synchronization, 0.3V is used as black level and 1V is used as a white level. Obviously almost any shade can be created by varying the voltage between the 0.3 and 1V levels, however for the simple display presented here black and white will suffice.

A video frame is made up from two fields of 312 scan lines displayed 25 times a second. For our purposes we will treat the odd and even fields as identical, this halves our vertical resolution but makes the design much simpler as we don't have to do interlacing, effectively therefore we are producing 312 scan lines 50 times a second giving a line rate of 15,600 lines per second (strictly speaking each frame has an additional line and the correct line rate is 15,625 however the missing 25 lines will not prove problematic in practice).

Each scan line lasts for 64μS and consists of a "front porch" of 2μS, a horizontal sync pulse of 4μS, a rear porch of 6μS and 52μS of displayed data. The diagram illustrates this along with a typical scan line waveform for some video bars.

PAL vsync waveform
The last part of the signal that needs explaining is the vertical synchronization that starts each field, the required waveform is shown in the diagram. Strictly speaking the second field of each frame should be a slightly different waveform, however in practice this doesn't seem necessary.


The proposed solution uses an external SRAM to hold the framebuffer data. The CPLD is used to generate appropriate timing to clock eight bits from the SRAM into the shift register every 500nS. A 256Kbit SRAM when clocked in this manner provides 256 64uS scan lines.

The shift register is clocked once every 62.5nS (16MHz rate) giving 1024bits per line, some of these bits will not be viewable as they are output during the boarders and sync times but a continuous clock greatly simplifies the design.

In addition to the SRAM clocking the CPLD generates the SYNC and BLANK signals to ensure the output waveform has sync and black levels at the appropriate times. The CPLD also generates the vertical synchronization waveform and ensures the top and bottom borders are black level.

The shift register output and the CPLD SYNC and BLANK signals are combined with AND gates to ensure correct output.

Data is written to the SRAM directly by the OKI CPU, the CPLD ensures correct timing and operation by using the CPU I/O wait function to delay access until the appropriate time.

Going further

Because the CPLD generates the vertical sync and can generate an interrupt it is possible to use a photodiode to detect the passing of the scanning beam (on a CRT) and calculate the time elapsed and hence the location of the photodiode on the screen. This would give a light pen function.

A possible extension of this circuit could be modified to detect sync pulses and capture an input waveform thus creating a simple framegrabber.


The schematic creates a specific design from the general ideas outlined previously. The design was generated directly by creating data, address and control buses and connecting the SRAM accordingly. Initially it was hoped the external shift register could be avoided by integrating it into the CPLD code, however CPLD resources were exhausted and this could not be achieved. The option was left for this mode of operation by adding R3 to the design to allow the CPLD CLK register to be used as the output instead.

The output from the shift register is combined with the SYNC and BLANK signals to allow the CPLD to gate the output data as appropriate. The 7408 device also serves as a buffer into the output load.

The resistor values for the output were carefully calculated to give the three needed output voltage levels when driven into a 75ohm impedance.

The SRAM appears twice so two footprints can be placed on the board in the PCB design. This allows for use of a variety of commonly available DIP and SOJ packaged SRAM .

After the design was created it was noted the use of HC series logic devices, which can be powered from a 3.3V supply, removes the need for a 5 Volt supply altogether. The output resistor values could simply be recomputed for a 3.3V levels.

The schematic was created with the "light" version of the Cadsoft EAGLE package. This schematic layout package was used to demonstrate what can be achieved with freely available software on a single page with the flexibility of the EB675001DIP module.

Shematic of the EB675001DIP video frambuffer application note The schematic was constructed using standard EAGLE library with a few additions

The complete schematic diagram is a straightforward layout as detailed above. Please refer to the documentation section for this schematic in several alternate formats


The main complexity in this project comes from the user CPLD which has to perform all the timing and control logic. The complete webpack project is available. The basic design consists of a vertical line counter which runs from 0 to 255 and is used for the upper seven bits of address to the SRAM and a second horizontal line counter which increments from 0 to 128 this is used as the bottom seven bits of the address output to the SRAM.

The horizontal counter is incremented every 500nS and the eight bits transferred into the shift register, comparators ensure the sync and porch signals are generated at the appropriate times, this has the effect of losing the first 21 and final 6 bytes of each line, this can easily be compensated for in software however and still gives over eight hundred horizontal bits worth of visible resolution (some bits may not be viewable on all TV sets as PAL signals are typically overscanned. Although losing 27 bytes per line may seem wasteful is massively simplifies the design and indeed means it will actually fit!

An additional processes are implemented to perform the shift register clocking. The original design intention did not include an external shift register but implemented the function within the CPLD. Because of space constraints in the CPLD this was not possible, a resistor option (R5) has been included in case this becomes possible in future.

Finally a process to arbitrate the CPU access to the SRAM, this logic decodes the CPU accesses in Chip Select Region 0 (CS0 is decoded to the memory area 0xF0000000 to 0xF0DFFFFF) and simply maps them through using the Wait line to hold the CPU access for the appropriate cycle length. Software should assume a 21byte offset to the start of the first displayed pixel, because most TVs underscan the data may not become visible until several pixels later in the line.

An pre built XSVF file is available for use with the PlayXSVF tool which allows for the CPLD to be programmed without any additional hardware.


Prototype video frambuffer project on maxtrix boardA prototype has been constructed using matrix wirewrap board.

Screen capture of the prototype output with insufficient power supply decoupling After the prototype was initially built we tested it by writing 0xff to all the SRAM hence setting the output to white. This was performed by using "memset 0xf0000000 0x8000 0xff" in ABLE. Instead of the expected bright white display a strange mottled effect was seen.

Diagram of oscilloscope waveform from the prototype output with incorrect power supply decouplingAn oscilloscope was connected to the composite output and a very strange waveform was observed. The diagram shows the expected waveform in black and the actual observed waveform in red (The diagram has been used because the actual scope image was not clear enough to use here). This shows an extensive drop in voltage during the 64μS that the circuit should have been outputting the 1V white level.

Screen capture of the prototype output with good power supply decoupling The scope probe was moved to examine the power supply and a voltage drop off almost exactly proportional to the one observed on the output was seen. This indicated there was not enough instantaneous power available. By adding more local decoupling capacitors and an additional 10μF bulk supply capacitor this effect was completely removed. This serves as an example of the need for good power supply design and layout in circuits such as these.

Oscilloscope capture of the prototype output with correct power supply decoupling This oscilloscope waveform was observed after the power supply changes. This waveform is almost identical to the expected shape and shows none of the "rolloff" seen previously.

PCB Design

The next step after a working prototype was to progress to a printed circuit board. Image of the video frambuffer appnotes pcb layoutthe PCB design was prepared in EAGLE. The main design parameters were :

because of this this board is straightforward to manufacture.

Many small run board houses will generate circuits directly from the eagle board file, please be sure to get the DC socket connections cut as slots (eagle does not have a way to directly specify this).

3D image of the video frambuffer appnotes pcb layoutA 3D povray model was created with Eagle 3D. This model is useful in designing enclosures and for visualizing the completed design.

Completed real AN0013 circuit boardOnce the design was fully visualized a small number of boards were purchased and assembled.

Assembly was performed along the usual lines, sockets first then resitors and capacitors then the voltage regulators. Before active components were added to the board the voltages were checked by probing the +3.3V and +5V points on the sockets. Then the active components were inserted and power applied.

It was soon discovered that the 3.3V requirements could be easily met with the regulator on-board the EB675001DIP module so the external regulator could be omitted further reducing component count.

The BOM for this project is relatively small, total cost should be around £20 excluding the EB675001DIP.

ReferenceValueGuide Pricing(£)Description
C1,C2,C3,C4,C7,C20100n0.305mm lead ceramic disc capacitor
C5,C6,C23,C2410u0.205mm lead polarised electrolytic capacitor
IC174HC165N0.30Eight bit shift register in DIL16 package.
SKT1DIL160.10DIL16 socket for IC1.
IC2,IC3BS62LV2563.00Two alternate footprints for a 256kBit SRAM, arranged as 32k x 8, a JC suffix indicates the SOJ28 package and the PC suffix is for the DIL28.1
IC474HC08N0.30Quad two input AND gates in DIL14 package.
SKT4DIL140.10DIL14 socket for IC4.
LED1,LED2L-934CB1ID 0.40Kingbright 3mm LED, alternately any normal LED adjusting R4,R7 to get correct current.
QG132.00MHz1.00Crystal resonator module in 8 pin DIL format.
R1470R0.051/8th watt 470 ohm thin film resistor.
R21K0.051/8th watt 1K ohm thin film resistor.
R4560R0.051/8th watt 560 ohm thin film resistor.
R568R0.051/8th watt 68 ohm thin film resistor.
R610k0.051/8th watt 10K ohm thin film resistor.
R7390R0.051/8th watt 390 ohm thin film resistor.
R84K70.051/8th watt 4K7 ohm thin film resistor.
RCA1RCA/PHONO0.60RCA phono socket
REG-5VLM1086VCT-5.02.00Low dropout 5V regulator in TO220 package.
S1B3F-31500.20Omron switch
SV3,SV4MA08-1W0.20Eight way pin headers
PCBPCB10.00Printed circuit board
MOD1EB675001DIP99.00EB675001DIP module

Note 1: Although the BSI SRAM is specified there are several pin compatible alternatives such as Integrated Device Technology IDT71V256SA20Y or Alliance Semiconductor AS7C3256A-12JCN.



Screen capture of the prototype output with ABLE framebuffer enabledTo ensure we have tested the hardware extensively an ABLE framebuffer driver was written and a special release built. This version MUST only be used with this application note!

ABLE is Simtec's next generation firmware. It is cross platform and is being actively developed for all Simtec boards. The ABLE resources section has more information and documentation.

The RAM loader version does not alter the flash contents of a module, however booting this version then running the romwrite version is useful to reprogram a module. Full details of bootstrapping a module are available in the Bootstrapping EB675001DIP document.

The current version of ABLE for the EB675001DIP AN0013 is 2.07 which is available in three binary packages.

Romwrite upgrade suitable if upgrading from a previous version of ABLE Binary file
Ram loader version suitable for booting a system using the downloader tool. Binary file
Raw binary suitable for programming with an EEPROM programmer Binary file
ABLE User Guide Hypertext markup file Portable Document File


Schematic diagram of the video framebuffer application notePDF filePNG image filePostscript fileEAGLE Schematic file

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