AN0004 - IDE interface for the EB675001DIP

Sections:

Introduction

Hardware

Introduction

This application note describes the addition of two parallel IDE chanels to the EB675001 Module. The ports are connected to the system by using the user CPLD which removes the need for any additional logic.

Hardware

Overview

The chosen design is two IDE connectors attached to the EB675001DIP module using its user programmable CPLD to perform all the necessary decode logic.

The two physical IDE connectors, one a 40 way 0.1inch pich standard connector, the other a 44 way 2mm laptop type connector. These ports are wired to the user CPLD lines via 22ohm buffer resistors.

The DASP and PDIAG lines are combined from both chanels to give an activity indicator. The system reset is brought to a switch to allow for a hard reset. The analog pins, power and I²C are also taken to a pin header for futher expansion.

Schematic

The schematic was created with the "light" version of the Cadsoft EAGLE package. This schematic layout package was used to demonstrate what can be achieved, even in a half size eurocard, with the flexibility of the EB675001DIP module.

The schematic was constructed using standard EAGLE library with a few additions

The complete schematic diagram is straightforward and adheres to the logical layout as described earlier (the documentation section has this schematic in several formats)

Board Design

Once the schematic was created a simple half eurocard size board was designed. For complete use of this design, within a standard eurocard enclosure, the EB675001DIP module should be ordered without its Ethernet and RS232 connectors fitted.

The main design parameters were :

Minimum track width of 0.3mm (approx 12mil)
Minimum track gap of 0.2mm (approx 8mil)
Simple two layer (top/bottom) design
Attempt to keep number of vias low
Use of inexpensive discreets

because of this this board should be relatively easy to manufacture hence reduce costs.

A complete archive of the generated Gerber has been produced for convenience.

A 3D povray model was created with Eagle 3D. This model is useful in designing enclosures and for visualising the completed design.

The complete partlist lists every component and its value.

Firmware

To interface the EB675001DIP to the quad serial circuit the user CPLD must be programmed with the appropriate logic. This logic must decode the correct address and chip selects from the OKI ML675001 into the correct address and read/write strobes to the IDE connectors.

The template VHDL EB675001DIP user CPLD project was copied and renamed. The decode logic was constructed and attached to the CPLD pins using the schematic as a reference. The complete project is available as well as the synthesised xsvf result. This code was uploaded and checked for correct operation using the peek and poke commands from ABLE.

For more details on programming the user CPLD please refer to the user CPLD section EB675001DIP resource page

Software

To use the ports in a familiar environment it was decided to modify μCLinux to support the ports. A simple patch to apply against the EB675001DIP μCLinux port was created. Once applied and the kernel and initrd rebuilt, the created image may be booted as explained in the μCLinux notes.

This patch allows access to two IDE ports, allowing up to four devices hda through hdd, as standard UNIX style block devices. The user space usage is beyond the scope of this application note.

Documentation

Schematic Diagram

Online Support

Disclaimer

Information contained in these publications regarding device applications and the like is intended as suggestion only and may be superseded by updates.

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