Timing Report

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Design Name template
Device, Speed (SpeedFile Version) XC9572XL, -7 (3.0)
Date Created Sat Jan 01 16:15:56 2000
Created By Timing Report Generator: version G.26
Copyright Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period 8.000 ns.
Max. Clock Frequency (fSYSTEM) 125.000 MHz.
Limited by Clock Pulse Width for cko_i
Clock to Setup (tCYC) 8.000 ns.
Pad to Pad Delay (tPD) 15.700 ns.
Setup to Clock at the Pad (tSU) 5.600 ns.
Clock Pad to Output Pad Delay (tCO) 12.700 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing



Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
cko_i 125.000 Limited by Clock Pulse Width for cko_i
nxoe_i 125.000 Limited by Clock Pulse Width for nxoe_i
nxwe_i 125.000 Limited by Clock Pulse Width for nxwe_i

Setup/Hold Times for Clocks

Setup/Hold Times for Clock nxoe_i
Source Pad Setup to clk (edge) Hold to clk (edge)
en<0> 4.800 0.000
en<1> 4.800 0.000
en<2> 4.800 0.000
en<3> 4.800 0.000
irq<0> 5.600 0.000
irq<1> 5.600 0.000
irq<2> 5.600 0.000
irq<3> 5.600 0.000
nrst_i 4.800 0.000
nxcs_i<2> 4.800 0.000
xa_i<21> 5.600 0.000
xa_i<22> 5.600 0.000
xa_i<23> 5.600 0.000

Setup/Hold Times for Clock nxwe_i
Source Pad Setup to clk (edge) Hold to clk (edge)
nrst_i 4.800 0.000
nxcs_i<2> 4.800 0.000
xa_i<21> 4.800 0.000
xa_i<22> 4.800 0.000
xa_i<23> 4.800 0.000
xd<0> 4.800 0.000
xd<1> 4.800 0.000
xd<2> 4.800 0.000
xd<3> 4.800 0.000
xd<4> 4.800 0.000
xd<5> 4.800 0.000
xd<6> 4.800 0.000
xd<7> 4.800 0.000


Clock to Pad Timing

Clock cko_i to Pad
Destination Pad Clock (edge) to Pad
clk_out 4.500

Clock nxoe_i to Pad
Destination Pad Clock (edge) to Pad
xd<0> 10.700
xd<1> 10.700
xd<2> 10.700
xd<3> 10.700
xd<4> 10.700
xd<5> 10.700
xd<6> 10.700
xd<7> 10.700

Clock nxwe_i to Pad
Destination Pad Clock (edge) to Pad
en<0> 12.700
en<1> 12.700
en<2> 12.700
en<3> 12.700
irq_out 11.500
led<0> 4.500
led<1> 4.500
led<2> 4.500
led<3> 4.500


Clock to Setup Times for Clocks

Clock to Setup for clock cko_i
Source Destination Delay
clk_counter<0>.Q clk_counter<1>.D 8.000
clk_counter<0>.Q clk_counter<2>.D 8.000
clk_counter<1>.Q clk_counter<2>.D 8.000
clk_counter<2>.Q clk_out.D 8.000


Pad to Pad List

Source Pad Destination Pad Delay
nlbs_i ext_data<0> 15.700
nlbs_i ext_data<1> 15.700
nlbs_i ext_data<2> 15.700
nlbs_i ext_data<3> 15.700
nlbs_i ext_data<4> 15.700
nlbs_i ext_data<5> 15.700
nlbs_i ext_data<6> 15.700
nlbs_i ext_data<7> 15.700
nlbs_i xd<0> 15.700
nlbs_i xd<1> 15.700
nlbs_i xd<2> 15.700
nlbs_i xd<3> 15.700
nlbs_i xd<4> 15.700
nlbs_i xd<5> 15.700
nlbs_i xd<6> 15.700
nlbs_i xd<7> 15.700
nubs_i ext_data<0> 15.700
nubs_i ext_data<1> 15.700
nubs_i ext_data<2> 15.700
nubs_i ext_data<3> 15.700
nubs_i ext_data<4> 15.700
nubs_i ext_data<5> 15.700
nubs_i ext_data<6> 15.700
nubs_i ext_data<7> 15.700
nxcs_i<2> xd<0> 15.700
nxcs_i<2> xd<1> 15.700
nxcs_i<2> xd<2> 15.700
nxcs_i<2> xd<3> 15.700
nxcs_i<2> xd<4> 15.700
nxcs_i<2> xd<5> 15.700
nxcs_i<2> xd<6> 15.700
nxcs_i<2> xd<7> 15.700
nxcs_i<3> ext_data<0> 15.700
nxcs_i<3> ext_data<1> 15.700
nxcs_i<3> ext_data<2> 15.700
nxcs_i<3> ext_data<3> 15.700
nxcs_i<3> ext_data<4> 15.700
nxcs_i<3> ext_data<5> 15.700
nxcs_i<3> ext_data<6> 15.700
nxcs_i<3> ext_data<7> 15.700
nxcs_i<3> xd<0> 15.700
nxcs_i<3> xd<1> 15.700
nxcs_i<3> xd<2> 15.700
nxcs_i<3> xd<3> 15.700
nxcs_i<3> xd<4> 15.700
nxcs_i<3> xd<5> 15.700
nxcs_i<3> xd<6> 15.700
nxcs_i<3> xd<7> 15.700
nxoe_i xd<0> 15.700
nxoe_i xd<1> 15.700
nxoe_i xd<2> 15.700
nxoe_i xd<3> 15.700
nxoe_i xd<4> 15.700
nxoe_i xd<5> 15.700
nxoe_i xd<6> 15.700
nxoe_i xd<7> 15.700
nxwe_i ext_data<0> 15.700
nxwe_i ext_data<1> 15.700
nxwe_i ext_data<2> 15.700
nxwe_i ext_data<3> 15.700
nxwe_i ext_data<4> 15.700
nxwe_i ext_data<5> 15.700
nxwe_i ext_data<6> 15.700
nxwe_i ext_data<7> 15.700
ncplden_i nbufen_io 9.500
nubs_i xd<10> 9.500
nubs_i xd<11> 9.500
nubs_i xd<12> 9.500
nubs_i xd<13> 9.500
nubs_i xd<14> 9.500
nubs_i xd<15> 9.500
nubs_i xd<8> 9.500
nubs_i xd<9> 9.500
nxcs_i<3> nbufen_io 9.500
nxcs_i<3> xd<10> 9.500
nxcs_i<3> xd<11> 9.500
nxcs_i<3> xd<12> 9.500
nxcs_i<3> xd<13> 9.500
nxcs_i<3> xd<14> 9.500
nxcs_i<3> xd<15> 9.500
nxcs_i<3> xd<8> 9.500
nxcs_i<3> xd<9> 9.500
nxoe_i xd<10> 9.500
nxoe_i xd<11> 9.500
nxoe_i xd<12> 9.500
nxoe_i xd<13> 9.500
nxoe_i xd<14> 9.500
nxoe_i xd<15> 9.500
nxoe_i xd<8> 9.500
nxoe_i xd<9> 9.500
irq<0> irq_out 8.300
xd<8> ext_data<0> 8.300
ext_data<0> xd<0> 7.500
ext_data<1> xd<1> 7.500
ext_data<2> xd<2> 7.500
ext_data<3> xd<3> 7.500
ext_data<4> xd<4> 7.500
ext_data<5> xd<5> 7.500
ext_data<6> xd<6> 7.500
ext_data<7> xd<7> 7.500
irq<1> irq_out 7.500
irq<2> irq_out 7.500
irq<3> irq_out 7.500
nrst_i rst_out 7.500
nwait_i xwait_o 7.500
nxcs_i<3> d_29 7.500
nxcs_i<3> iord 7.500
nxcs_i<3> iowr 7.500
nxcs_i<3> ucs<0> 7.500
nxcs_i<3> ucs<1> 7.500
nxcs_i<3> ucs<2> 7.500
nxcs_i<3> ucs<3> 7.500
nxoe_i iord 7.500
nxwe_i iowr 7.500
xa0_i d_29 7.500
xa_i<21> ucs<0> 7.500
xa_i<21> ucs<1> 7.500
xa_i<21> ucs<2> 7.500
xa_i<21> ucs<3> 7.500
xa_i<22> ucs<0> 7.500
xa_i<22> ucs<1> 7.500
xa_i<22> ucs<2> 7.500
xa_i<22> ucs<3> 7.500
xa_i<23> ucs<0> 7.500
xa_i<23> ucs<1> 7.500
xa_i<23> ucs<2> 7.500
xa_i<23> ucs<3> 7.500
xd<10> ext_data<2> 7.500
xd<11> ext_data<3> 7.500
xd<12> ext_data<4> 7.500
xd<13> ext_data<5> 7.500
xd<14> ext_data<6> 7.500
xd<15> ext_data<7> 7.500
xd<9> ext_data<1> 7.500
xd<0> ext_data<0> 6.000
ext_data<0> xd<8> 5.200
ext_data<1> xd<9> 5.200
ext_data<2> xd<10> 5.200
ext_data<3> xd<11> 5.200
ext_data<4> xd<12> 5.200
ext_data<5> xd<13> 5.200
ext_data<6> xd<14> 5.200
ext_data<7> xd<15> 5.200
xd<1> ext_data<1> 5.200
xd<2> ext_data<2> 5.200
xd<3> ext_data<3> 5.200
xd<4> ext_data<4> 5.200
xd<5> ext_data<5> 5.200
xd<6> ext_data<6> 5.200
xd<7> ext_data<7> 5.200


Number of paths analyzed: 0
Number of Timing errors: 0
Analysis Completed: Sat Jan 01 16:15:56 2000