cpldfit: version G.26 Xilinx Inc. Fitter Report Design Name: template Date: 1- 1-2000, 4:15PM Device Used: XC9572XL-7-TQ100 Fitting Status: Successful **************************** Resource Summary **************************** Macrocells Product Terms Registers Pins Function Block Used Used Used Used Inputs Used 65 /72 ( 90%) 183 /360 ( 51%) 28 /72 ( 39%) 62 /72 ( 86%) 107/216 ( 50%) PIN RESOURCES: Signal Type Required Mapped | Pin Type Used Remaining ------------------------------------|--------------------------------------- Input : 14 14 | I/O : 57 9 Output : 16 16 | GCK/IO : 3 0 Bidirectional : 28 28 | GTS/IO : 1 1 GCK : 3 3 | GSR/IO : 1 0 GTS : 0 0 | GSR : 1 1 | ---- ---- Total 62 62 MACROCELL RESOURCES: Total Macrocells Available 72 Registered Macrocells 28 Non-registered Macrocell driving I/O 35 GLOBAL RESOURCES: Signal 'nxwe_i' mapped onto global clock net GCK1. Signal 'nxoe_i' mapped onto global clock net GCK2. Signal 'cko_i' mapped onto global clock net GCK3. Global output enable net(s) unused. Signal 'nrst_i' mapped onto global set/reset net GSR. POWER DATA: There are 65 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). There are a total of 65 macrocells used (MC). End of Resource Summary *************** Summary of Required Resources ****************** ** LOGIC ** Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init Name Pt Used Mode Rate # Type Use State clk_counter<0> 0 0 FB3_4 STD 50 I/O I RESET clk_counter<1> 1 1 FB3_3 STD 49 I/O I RESET clk_counter<2> 1 2 FB3_2 STD 32 I/O I RESET clk_out 1 1 FB4_1 STD FAST 65 I/O O RESET d_29 1 2 FB3_7 STD FAST 54 I/O O en<0> 3 7 FB2_1 STD FAST 87 I/O I/O RESET en<1> 3 7 FB2_8 STD FAST 97 I/O I/O RESET en<2> 3 7 FB2_11 STD FAST 4 GTS/I/O I/O RESET en<3> 3 7 FB3_14 STD FAST 55 I/O I/O RESET en_ctrl<0> 2 6 FB4_18 STD 79 I/O I RESET en_ctrl<1> 2 6 FB4_16 STD 86 I/O (b) RESET en_ctrl<2> 2 6 FB4_13 STD 85 I/O (b) RESET en_ctrl<3> 2 6 FB4_12 STD 82 I/O (b) RESET ext_data<0> 5 6 FB3_16 STD FAST 64 I/O I/O ext_data<1> 5 6 FB4_2 STD FAST 67 I/O I/O ext_data<2> 5 6 FB4_9 STD FAST 66 I/O I/O ext_data<3> 5 6 FB4_8 STD FAST 70 I/O I/O ext_data<4> 5 6 FB4_5 STD FAST 68 I/O I/O ext_data<5> 5 6 FB4_4 STD FAST 72 I/O I/O ext_data<6> 5 6 FB4_3 STD FAST 71 I/O I/O ext_data<7> 5 6 FB4_6 STD FAST 76 I/O I/O ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST 2 4 FB3_11 STD 52 I/O I iord 1 2 FB3_18 STD FAST 59 I/O O iowr 1 2 FB4_7 STD FAST 77 I/O O irq_en<0> 2 5 FB2_9 STD 99 GSR/I/O GSR/I RESET irq_en<1> 2 5 FB2_7 STD 3 GTS/I/O (b) RESET irq_en<2> 2 5 FB2_6 STD 96 I/O (b) RESET irq_en<3> 2 5 FB4_11 STD 74 I/O I RESET irq_out 4 8 FB2_13 STD FAST 8 I/O O led<0> 2 6 FB2_18 STD FAST 92 I/O O RESET led<1> 2 6 FB2_3 STD FAST 91 I/O O RESET led<2> 2 6 FB4_15 STD FAST 89 I/O O RESET led<3> 2 6 FB4_17 STD FAST 90 I/O O RESET nbufen_io 1 2 FB1_10 STD FAST 28 I/O O rst_out 1 1 FB3_12 STD FAST 61 I/O O ucs<0> 1 4 FB4_10 STD FAST 81 I/O O ucs<1> 1 4 FB4_14 STD FAST 78 I/O O ucs<2> 1 4 FB3_10 STD FAST 60 I/O O ucs<3> 1 4 FB3_17 STD FAST 58 I/O O user_bus<0> 7 10 FB2_16 STD 10 I/O I RESET user_bus<1> 7 10 FB2_14 STD 9 I/O I RESET user_bus<2> 7 10 FB3_15 STD 56 I/O I RESET user_bus<3> 7 10 FB3_13 STD 63 I/O I RESET user_bus<4> 2 6 FB2_5 STD 95 I/O (b) RESET user_bus<5> 3 6 FB2_12 STD 6 I/O (b) RESET user_bus<6> 2 6 FB2_4 STD 93 I/O (b) RESET user_bus<7> 3 6 FB2_10 STD 1 I/O (b) RESET xd<0> 4 5 FB1_3 STD FAST 18 I/O I/O xd<10> 2 4 FB1_13 STD FAST 36 I/O I/O xd<11> 2 4 FB3_8 STD FAST 37 I/O I/O xd<12> 2 4 FB1_16 STD FAST 39 I/O I/O xd<13> 2 4 FB1_18 STD FAST 40 I/O I/O xd<14> 2 4 FB3_1 STD FAST 41 I/O I/O xd<15> 2 4 FB3_9 STD FAST 42 I/O I/O xd<1> 4 5 FB1_8 STD FAST 17 I/O I/O xd<2> 4 5 FB1_1 STD FAST 16 I/O I/O xd<3> 4 5 FB1_6 STD FAST 15 I/O I/O xd<4> 4 5 FB1_5 STD FAST 14 I/O I/O xd<5> 4 5 FB1_2 STD FAST 13 I/O I/O xd<6> 4 5 FB2_17 STD FAST 12 I/O I/O xd<7> 4 5 FB2_15 STD FAST 11 I/O I/O xd<8> 2 4 FB1_12 STD FAST 33 I/O I/O xd<9> 2 4 FB3_5 STD FAST 35 I/O I/O xd_0_IOBUFE/xd_0_IOBUFE_TRST 2 4 FB3_6 STD 53 I/O I xwait_o 1 1 FB1_7 STD FAST 25 I/O O ** INPUTS ** Signal Loc Pin Pin Pin Name # Type Use cko_i FB1_14 27 GCK/I/O GCK irq<0> FB4_11 74 I/O I irq<1> FB4_18 79 I/O I irq<2> FB3_13 63 I/O I irq<3> FB3_15 56 I/O I ncplden_i FB1_15 29 I/O I nlbs_i FB3_2 32 I/O I nrst_i FB2_9 99 GSR/I/O GSR/I nubs_i FB1_17 30 I/O I nwait_i FB1_4 20 I/O I nxcs_i<2> FB2_16 10 I/O I nxcs_i<3> FB2_14 9 I/O I nxoe_i FB1_11 23 GCK/I/O GCK/I nxwe_i FB1_9 22 GCK/I/O GCK/I xa0_i FB3_3 49 I/O I xa_i<21> FB3_4 50 I/O I xa_i<22> FB3_11 52 I/O I xa_i<23> FB3_6 53 I/O I End of Resources *********************Function Block Resource Summary*********************** Function # of FB Inputs Signals Total O/IO IO Block Macrocells Used Used Pt Used Req Avail FB1 12 19 19 34 2/10 18 FB2 17 32 32 55 3/5 18 FB3 18 32 32 41 5/6 18 FB4 18 24 24 53 6/7 18 ---- ----- ----- ----- 65 183 16/28 72 *********************************** FB1 *********************************** Number of function block inputs used/remaining: 19/35 Number of signals used by logic mapping into function block: 19 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use xd<2> 4 0 0 1 FB1_1 STD 16 I/O I/O xd<5> 4 0 0 1 FB1_2 STD 13 I/O I/O xd<0> 4 0 0 1 FB1_3 STD 18 I/O I/O (unused) 0 0 0 5 FB1_4 20 I/O I xd<4> 4 0 0 1 FB1_5 STD 14 I/O I/O xd<3> 4 0 0 1 FB1_6 STD 15 I/O I/O xwait_o 1 0 0 4 FB1_7 STD 25 I/O O xd<1> 4 0 0 1 FB1_8 STD 17 I/O I/O (unused) 0 0 0 5 FB1_9 22 GCK/I/O GCK/I nbufen_io 1 0 0 4 FB1_10 STD 28 I/O O (unused) 0 0 0 5 FB1_11 23 GCK/I/O GCK/I xd<8> 2 0 0 3 FB1_12 STD 33 I/O I/O xd<10> 2 0 0 3 FB1_13 STD 36 I/O I/O (unused) 0 0 0 5 FB1_14 27 GCK/I/O GCK (unused) 0 0 0 5 FB1_15 29 I/O I xd<12> 2 0 0 3 FB1_16 STD 39 I/O I/O (unused) 0 0 0 5 FB1_17 30 I/O I xd<13> 2 0 0 3 FB1_18 STD 40 I/O I/O Signals Used by Logic in Function Block 1: ncplden_i 8: user_bus<1> 14: ext_data<2>.PIN 2: nubs_i 9: user_bus<2> 15: ext_data<3>.PIN 3: nwait_i 10: user_bus<3> 16: ext_data<4>.PIN 4: nxcs_i<2> 11: user_bus<4> 17: ext_data<5>.PIN 5: nxcs_i<3> 12: user_bus<5> 18: ext_data<0>.PIN 6: nxoe_i 13: xd_0_IOBUFE/xd_0_IOBUFE_TRST 19: ext_data<1>.PIN 7: user_bus<0> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs xd<2> ...X.X..X...XX.......................... 5 5 xd<5> ...X.X.....XX...X....................... 5 5 xd<0> ...X.XX.....X....X...................... 5 5 xd<4> ...X.X....X.X..X........................ 5 5 xd<3> ...X.X...X..X.X......................... 5 5 xwait_o ..X..................................... 1 1 xd<1> ...X.X.X....X.....X..................... 5 5 nbufen_io X...X................................... 2 2 xd<8> .X..XX...........X...................... 4 4 xd<10> .X..XX.......X.......................... 4 4 xd<12> .X..XX.........X........................ 4 4 xd<13> .X..XX..........X....................... 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB2 *********************************** Number of function block inputs used/remaining: 32/22 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use en<0> 3 0 0 2 FB2_1 STD 87 I/O I/O (unused) 0 0 0 5 FB2_2 94 I/O led<1> 2 0 0 3 FB2_3 STD 91 I/O O user_bus<6> 2 0 0 3 FB2_4 STD 93 I/O (b) user_bus<4> 2 0 0 3 FB2_5 STD 95 I/O (b) irq_en<2> 2 0 0 3 FB2_6 STD 96 I/O (b) irq_en<1> 2 0 0 3 FB2_7 STD 3 GTS/I/O (b) en<1> 3 0 0 2 FB2_8 STD 97 I/O I/O irq_en<0> 2 0 0 3 FB2_9 STD 99 GSR/I/O GSR/I user_bus<7> 3 0 0 2 FB2_10 STD 1 I/O (b) en<2> 3 0 0 2 FB2_11 STD 4 GTS/I/O I/O user_bus<5> 3 0 \/1 1 FB2_12 STD 6 I/O (b) irq_out 4 1<- \/2 0 FB2_13 STD 8 I/O O user_bus<1> 7 2<- 0 0 FB2_14 STD 9 I/O I xd<7> 4 0 \/1 0 FB2_15 STD 11 I/O I/O user_bus<0> 7 2<- 0 0 FB2_16 STD 10 I/O I xd<6> 4 0 /\1 0 FB2_17 STD 12 I/O I/O led<0> 2 0 0 3 FB2_18 STD 92 I/O O Signals Used by Logic in Function Block 1: en<0>.PIN 12: irq<0> 23: nxcs_i<2> 2: en<1>.PIN 13: irq<1> 24: nxoe_i 3: xd<0>.PIN 14: irq<2> 25: user_bus<6> 4: xd<1>.PIN 15: irq<3> 26: user_bus<7> 5: xd<2>.PIN 16: irq_en<0> 27: xa_i<21> 6: en<0> 17: irq_en<1> 28: xa_i<22> 7: en<1> 18: irq_en<2> 29: xa_i<23> 8: en_ctrl<0> 19: irq_en<3> 30: xd_0_IOBUFE/xd_0_IOBUFE_TRST 9: en_ctrl<1> 20: led<0> 31: ext_data<6>.PIN 10: en_ctrl<2> 21: led<1> 32: ext_data<7>.PIN 11: en_ctrl<3> 22: nrst_i Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs en<0> ..X....X.............XX...XXX........... 7 7 led<1> ...X.................XX...XXX........... 6 6 user_bus<6> .........X...........XX...XXX........... 6 6 user_bus<4> .......X.............XX...XXX........... 6 6 irq_en<2> ....X.................X...XXX........... 5 5 irq_en<1> ...X..................X...XXX........... 5 5 en<1> ...X....X............XX...XXX........... 7 7 irq_en<0> ..X...................X...XXX........... 5 5 user_bus<7> ..........X..........XX...XXX........... 6 6 en<2> ....X....X...........XX...XXX........... 7 7 user_bus<5> ........X............XX...XXX........... 6 6 irq_out ...........XXXXXXXX..................... 8 8 user_bus<1> .X....X.....X...X...XXX...XXX........... 10 10 xd<7> ......................XX.X...X.X........ 5 5 user_bus<0> X....X.....X...X...X.XX...XXX........... 10 10 xd<6> ......................XXX....XX......... 5 5 led<0> ..X..................XX...XXX........... 6 6 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB3 *********************************** Number of function block inputs used/remaining: 32/22 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use xd<14> 2 0 0 3 FB3_1 STD 41 I/O I/O clk_counter<2> 1 0 0 4 FB3_2 STD 32 I/O I clk_counter<1> 1 0 0 4 FB3_3 STD 49 I/O I clk_counter<0> 0 0 0 5 FB3_4 STD 50 I/O I xd<9> 2 0 0 3 FB3_5 STD 35 I/O I/O xd_0_IOBUFE/xd_0_IOBUFE_TRST 2 0 0 3 FB3_6 STD 53 I/O I d_29 1 0 0 4 FB3_7 STD 54 I/O O xd<11> 2 0 0 3 FB3_8 STD 37 I/O I/O xd<15> 2 0 0 3 FB3_9 STD 42 I/O I/O ucs<2> 1 0 0 4 FB3_10 STD 60 I/O O ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST 2 0 0 3 FB3_11 STD 52 I/O I rst_out 1 0 \/1 3 FB3_12 STD 61 I/O O user_bus<3> 7 2<- 0 0 FB3_13 STD 63 I/O I en<3> 3 0 /\1 1 FB3_14 STD 55 I/O I/O user_bus<2> 7 2<- 0 0 FB3_15 STD 56 I/O I ext_data<0> 5 2<- /\2 0 FB3_16 STD 64 I/O I/O ucs<3> 1 0 /\2 2 FB3_17 STD 58 I/O O iord 1 0 0 4 FB3_18 STD 59 I/O O Signals Used by Logic in Function Block 1: xd<0>.PIN 12: irq<2> 23: nxoe_i 2: en<2>.PIN 13: irq<3> 24: nxwe_i 3: en<3>.PIN 14: irq_en<2> 25: xa0_i 4: xd<3>.PIN 15: irq_en<3> 26: xa_i<21> 5: xd<8>.PIN 16: led<2> 27: xa_i<22> 6: clk_counter<0> 17: led<3> 28: xa_i<23> 7: clk_counter<1> 18: nlbs_i 29: ext_data<3>.PIN 8: en<2> 19: nrst_i 30: ext_data<6>.PIN 9: en<3> 20: nubs_i 31: ext_data<7>.PIN 10: en_ctrl<3> 21: nxcs_i<2> 32: ext_data<1>.PIN 11: ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST 22: nxcs_i<3> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs xd<14> ...................X.XX......X.......... 4 4 clk_counter<2> .....XX................................. 2 2 clk_counter<1> .....X.................................. 1 1 clk_counter<0> ........................................ 0 0 xd<9> ...................X.XX........X........ 4 4 xd_0_IOBUFE/xd_0_IOBUFE_TRST .................X..XXX................. 4 4 d_29 .....................X..X............... 2 2 xd<11> ...................X.XX.....X........... 4 4 xd<15> ...................X.XX.......X......... 4 4 ucs<2> .....................X...XXX............ 4 4 ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST .................X.X.X.X................ 4 4 rst_out ..................X..................... 1 1 user_bus<3> ..X.....X...X.X.X.X.X....XXX............ 10 10 en<3> ...X.....X........X.X....XXX............ 7 7 user_bus<2> .X.....X...X.X.X..X.X....XXX............ 10 10 ext_data<0> X...X.....X......X...X.X................ 6 6 ucs<3> .....................X...XXX............ 4 4 iord .....................XX................. 2 2 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB4 *********************************** Number of function block inputs used/remaining: 24/30 Number of signals used by logic mapping into function block: 24 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use clk_out 1 0 0 4 FB4_1 STD 65 I/O O ext_data<1> 5 0 0 0 FB4_2 STD 67 I/O I/O ext_data<6> 5 0 0 0 FB4_3 STD 71 I/O I/O ext_data<5> 5 0 0 0 FB4_4 STD 72 I/O I/O ext_data<4> 5 0 0 0 FB4_5 STD 68 I/O I/O ext_data<7> 5 0 0 0 FB4_6 STD 76 I/O I/O iowr 1 0 0 4 FB4_7 STD 77 I/O O ext_data<3> 5 0 0 0 FB4_8 STD 70 I/O I/O ext_data<2> 5 0 0 0 FB4_9 STD 66 I/O I/O ucs<0> 1 0 0 4 FB4_10 STD 81 I/O O irq_en<3> 2 0 0 3 FB4_11 STD 74 I/O I en_ctrl<3> 2 0 0 3 FB4_12 STD 82 I/O (b) en_ctrl<2> 2 0 0 3 FB4_13 STD 85 I/O (b) ucs<1> 1 0 0 4 FB4_14 STD 78 I/O O led<2> 2 0 0 3 FB4_15 STD 89 I/O O en_ctrl<1> 2 0 0 3 FB4_16 STD 86 I/O (b) led<3> 2 0 0 3 FB4_17 STD 90 I/O O en_ctrl<0> 2 0 0 3 FB4_18 STD 79 I/O I Signals Used by Logic in Function Block 1: xd<1>.PIN 9: xd<10>.PIN 17: nlbs_i 2: xd<2>.PIN 10: xd<11>.PIN 18: nrst_i 3: xd<3>.PIN 11: xd<12>.PIN 19: nxcs_i<2> 4: xd<4>.PIN 12: xd<13>.PIN 20: nxcs_i<3> 5: xd<5>.PIN 13: xd<14>.PIN 21: nxwe_i 6: xd<6>.PIN 14: xd<15>.PIN 22: xa_i<21> 7: xd<7>.PIN 15: clk_counter<2> 23: xa_i<22> 8: xd<9>.PIN 16: ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST 24: xa_i<23> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs clk_out ..............X......................... 1 1 ext_data<1> X......X.......XX..XX................... 6 6 ext_data<6> .....X......X..XX..XX................... 6 6 ext_data<5> ....X......X...XX..XX................... 6 6 ext_data<4> ...X......X....XX..XX................... 6 6 ext_data<7> ......X......X.XX..XX................... 6 6 iowr ...................XX................... 2 2 ext_data<3> ..X......X.....XX..XX................... 6 6 ext_data<2> .X......X......XX..XX................... 6 6 ucs<0> ...................X.XXX................ 4 4 irq_en<3> ..X...............X..XXX................ 5 5 en_ctrl<3> ......X..........XX..XXX................ 6 6 en_ctrl<2> .....X...........XX..XXX................ 6 6 ucs<1> ...................X.XXX................ 4 4 led<2> .X...............XX..XXX................ 6 6 en_ctrl<1> ....X............XX..XXX................ 6 6 led<3> ..X..............XX..XXX................ 6 6 en_ctrl<0> ...X.............XX..XXX................ 6 6 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. ;;-----------------------------------------------------------------;; ; Implemented Equations. clk_counter<0>.T = Vcc; clk_counter<0>.CLK = cko_i; // GCK clk_counter<1>.T = clk_counter<0>; clk_counter<1>.CLK = cko_i; // GCK clk_counter<2>.T = clk_counter<0> & clk_counter<1>; clk_counter<2>.CLK = cko_i; // GCK d_29 = !nxcs_i<3> & xa0_i; en_ctrl<0>.D = xd<4>.PIN; en_ctrl<0>.CLK = nxwe_i; // GCK en_ctrl<0>.CE = !xa_i<21> & xa_i<23> & xa_i<22> & !nxcs_i<2> & nrst_i; en_ctrl<1>.D = xd<5>.PIN; en_ctrl<1>.CLK = nxwe_i; // GCK en_ctrl<1>.CE = !xa_i<21> & xa_i<23> & xa_i<22> & !nxcs_i<2> & nrst_i; en_ctrl<2>.D = xd<6>.PIN; en_ctrl<2>.CLK = nxwe_i; // GCK en_ctrl<2>.CE = !xa_i<21> & xa_i<23> & xa_i<22> & !nxcs_i<2> & nrst_i; en_ctrl<3>.D = xd<7>.PIN; en_ctrl<3>.CLK = nxwe_i; // GCK en_ctrl<3>.CE = !xa_i<21> & xa_i<23> & xa_i<22> & !nxcs_i<2> & nrst_i; en<0>.D = xd<0>.PIN; en<0>.CLK = nxwe_i; // GCK en<0>.OE = en_ctrl<0>; en<0>.CE = !xa_i<21> & xa_i<23> & xa_i<22> & !nxcs_i<2> & nrst_i; en<1>.D = xd<1>.PIN; en<1>.CLK = nxwe_i; // GCK en<1>.OE = en_ctrl<1>; en<1>.CE = !xa_i<21> & xa_i<23> & xa_i<22> & !nxcs_i<2> & nrst_i; en<2>.D = xd<2>.PIN; en<2>.CLK = nxwe_i; // GCK en<2>.OE = en_ctrl<2>; en<2>.CE = !xa_i<21> & xa_i<23> & xa_i<22> & !nxcs_i<2> & nrst_i; en<3>.D = xd<3>.PIN; en<3>.CLK = nxwe_i; // GCK en<3>.OE = en_ctrl<3>; en<3>.CE = !xa_i<21> & xa_i<23> & xa_i<22> & !nxcs_i<2> & nrst_i; ext_data<0> = nxwe_i & xd<8>.PIN # nxcs_i<3> & xd<8>.PIN ;Imported pterms FB3_17 # nlbs_i & xd<8>.PIN # xd<0>.PIN & !nxwe_i & !nxcs_i<3> & !nlbs_i; ext_data<0>.OE = ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST; ext_data<1> = nxwe_i & xd<9>.PIN # nxcs_i<3> & xd<9>.PIN # nlbs_i & xd<9>.PIN # !nxwe_i & xd<1>.PIN & !nxcs_i<3> & !nlbs_i; ext_data<1>.OE = ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST; ext_data<2> = nxwe_i & xd<10>.PIN # nxcs_i<3> & xd<10>.PIN # nlbs_i & xd<10>.PIN # !nxwe_i & xd<2>.PIN & !nxcs_i<3> & !nlbs_i; ext_data<2>.OE = ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST; ext_data<3> = nxwe_i & xd<11>.PIN # nxcs_i<3> & xd<11>.PIN # nlbs_i & xd<11>.PIN # !nxwe_i & xd<3>.PIN & !nxcs_i<3> & !nlbs_i; ext_data<3>.OE = ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST; ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST = !nxwe_i & !nxcs_i<3> & !nlbs_i # !nxwe_i & !nxcs_i<3> & !nubs_i; ext_data<4> = nxwe_i & xd<12>.PIN # nxcs_i<3> & xd<12>.PIN # nlbs_i & xd<12>.PIN # !nxwe_i & !nxcs_i<3> & !nlbs_i & xd<4>.PIN; ext_data<4>.OE = ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST; ext_data<5> = nxwe_i & xd<13>.PIN # nxcs_i<3> & xd<13>.PIN # nlbs_i & xd<13>.PIN # !nxwe_i & !nxcs_i<3> & !nlbs_i & xd<5>.PIN; ext_data<5>.OE = ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST; ext_data<6> = nxwe_i & xd<14>.PIN # nxcs_i<3> & xd<14>.PIN # nlbs_i & xd<14>.PIN # !nxwe_i & !nxcs_i<3> & !nlbs_i & xd<6>.PIN; ext_data<6>.OE = ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST; ext_data<7> = nxwe_i & xd<15>.PIN # nxcs_i<3> & xd<15>.PIN # nlbs_i & xd<15>.PIN # !nxwe_i & !nxcs_i<3> & !nlbs_i & xd<7>.PIN; ext_data<7>.OE = ext_data_3_IOBUFE/ext_data_3_IOBUFE_TRST; !iord = !nxcs_i<3> & !nxoe_i; !iowr = !nxwe_i & !nxcs_i<3>; irq_en<0>.D = xd<0>.PIN; irq_en<0>.CLK = nxwe_i; // GCK !irq_en<0>.AR = nrst_i; // GSR irq_en<0>.CE = xa_i<21> & !xa_i<23> & !xa_i<22> & !nxcs_i<2>; irq_en<1>.D = xd<1>.PIN; irq_en<1>.CLK = nxwe_i; // GCK !irq_en<1>.AR = nrst_i; // GSR irq_en<1>.CE = xa_i<21> & !xa_i<23> & !xa_i<22> & !nxcs_i<2>; irq_en<2>.D = xd<2>.PIN; irq_en<2>.CLK = nxwe_i; // GCK !irq_en<2>.AR = nrst_i; // GSR irq_en<2>.CE = xa_i<21> & !xa_i<23> & !xa_i<22> & !nxcs_i<2>; irq_en<3>.D = xd<3>.PIN; irq_en<3>.CLK = nxwe_i; // GCK !irq_en<3>.AR = nrst_i; // GSR irq_en<3>.CE = xa_i<21> & !xa_i<23> & !xa_i<22> & !nxcs_i<2>; !irq_out = irq_en<1> & irq<1> # irq_en<2> & irq<2> # irq_en<3> & irq<3> ;Imported pterms FB2_12 # irq_en<0> & irq<0>; led<0>.D = xd<0>.PIN; led<0>.CLK = nxwe_i; // GCK led<0>.CE = !xa_i<21> & xa_i<23> & !xa_i<22> & !nxcs_i<2> & nrst_i; led<1>.D = xd<1>.PIN; led<1>.CLK = nxwe_i; // GCK led<1>.CE = !xa_i<21> & xa_i<23> & !xa_i<22> & !nxcs_i<2> & nrst_i; led<2>.D = xd<2>.PIN; led<2>.CLK = nxwe_i; // GCK led<2>.CE = !xa_i<21> & xa_i<23> & !xa_i<22> & !nxcs_i<2> & nrst_i; led<3>.D = xd<3>.PIN; led<3>.CLK = nxwe_i; // GCK led<3>.CE = !xa_i<21> & xa_i<23> & !xa_i<22> & !nxcs_i<2> & nrst_i; nbufen_io = Gnd; !nbufen_io.OE = nxcs_i<3> & ncplden_i; rst_out = !nrst_i; clk_out.D = clk_counter<2>; clk_out.CLK = cko_i; // GCK !ucs<0> = !xa_i<21> & !xa_i<23> & !xa_i<22> & !nxcs_i<3>; !ucs<1> = xa_i<21> & !xa_i<23> & !xa_i<22> & !nxcs_i<3>; !ucs<2> = !xa_i<21> & !xa_i<23> & xa_i<22> & !nxcs_i<3>; !ucs<3> = xa_i<21> & !xa_i<23> & xa_i<22> & !nxcs_i<3>; user_bus<0>.D = en<0> & !xa_i<21> & xa_i<23> & xa_i<22> # xa_i<21> & xa_i<23> & !xa_i<22> & en<0>.PIN # xa_i<21> & !xa_i<23> & !xa_i<22> & irq_en<0> # !xa_i<21> & xa_i<23> & !xa_i<22> & led<0> ;Imported pterms FB2_15 # !xa_i<21> & !xa_i<23> & xa_i<22> & irq<0> ;Imported pterms FB2_17 # !xa_i<23> & xa_i<22> & irq_en<0> & irq<0>; !user_bus<0>.CLK = nxoe_i; // GCK user_bus<0>.CE = !nxcs_i<2> & nrst_i; user_bus<1>.D = en<1> & !xa_i<21> & xa_i<23> & xa_i<22> # xa_i<21> & xa_i<23> & !xa_i<22> & en<1>.PIN # xa_i<21> & !xa_i<23> & !xa_i<22> & irq_en<1> # !xa_i<21> & xa_i<23> & !xa_i<22> & led<1> ;Imported pterms FB2_13 # !xa_i<21> & !xa_i<23> & xa_i<22> & irq<1> # !xa_i<23> & xa_i<22> & irq_en<1> & irq<1>; !user_bus<1>.CLK = nxoe_i; // GCK user_bus<1>.CE = !nxcs_i<2> & nrst_i; user_bus<2>.D = en<2> & !xa_i<21> & xa_i<23> & xa_i<22> # xa_i<21> & xa_i<23> & !xa_i<22> & en<2>.PIN # xa_i<21> & !xa_i<23> & !xa_i<22> & irq_en<2> # !xa_i<21> & xa_i<23> & !xa_i<22> & led<2> ;Imported pterms FB3_16 # !xa_i<21> & !xa_i<23> & xa_i<22> & irq<2> # !xa_i<23> & xa_i<22> & irq_en<2> & irq<2>; !user_bus<2>.CLK = nxoe_i; // GCK user_bus<2>.CE = !nxcs_i<2> & nrst_i; user_bus<3>.D = en<3> & !xa_i<21> & xa_i<23> & xa_i<22> # xa_i<21> & xa_i<23> & !xa_i<22> & en<3>.PIN # xa_i<21> & !xa_i<23> & !xa_i<22> & irq_en<3> # !xa_i<21> & xa_i<23> & !xa_i<22> & led<3> ;Imported pterms FB3_12 # !xa_i<21> & !xa_i<23> & xa_i<22> & irq<3> ;Imported pterms FB3_14 # !xa_i<23> & xa_i<22> & irq_en<3> & irq<3>; !user_bus<3>.CLK = nxoe_i; // GCK user_bus<3>.CE = !nxcs_i<2> & nrst_i; user_bus<4>.D = !xa_i<21> & xa_i<23> & xa_i<22> & en_ctrl<0>; !user_bus<4>.CLK = nxoe_i; // GCK user_bus<4>.CE = !nxcs_i<2> & nrst_i; user_bus<5>.D = !xa_i<21> & !xa_i<23> & !xa_i<22> # !xa_i<21> & xa_i<23> & xa_i<22> & en_ctrl<1>; !user_bus<5>.CLK = nxoe_i; // GCK user_bus<5>.CE = !nxcs_i<2> & nrst_i; user_bus<6>.D = !xa_i<21> & xa_i<23> & xa_i<22> & en_ctrl<2>; !user_bus<6>.CLK = nxoe_i; // GCK user_bus<6>.CE = !nxcs_i<2> & nrst_i; user_bus<7>.D = !xa_i<21> & !xa_i<23> & !xa_i<22> # !xa_i<21> & xa_i<23> & xa_i<22> & en_ctrl<3>; !user_bus<7>.CLK = nxoe_i; // GCK user_bus<7>.CE = !nxcs_i<2> & nrst_i; xd<0> = nxcs_i<2> & ext_data<0>.PIN # nxoe_i & ext_data<0>.PIN # !nxcs_i<2> & !nxoe_i & user_bus<0>; xd<0>.OE = xd_0_IOBUFE/xd_0_IOBUFE_TRST; xd_0_IOBUFE/xd_0_IOBUFE_TRST = !nxcs_i<2> & !nxoe_i # !nxcs_i<3> & !nlbs_i & !nxoe_i; xd<10> = ext_data<2>.PIN; xd<10>.OE = !nxcs_i<3> & !nxoe_i & !nubs_i; xd<11> = ext_data<3>.PIN; xd<11>.OE = !nxcs_i<3> & !nxoe_i & !nubs_i; xd<12> = ext_data<4>.PIN; xd<12>.OE = !nxcs_i<3> & !nxoe_i & !nubs_i; xd<13> = ext_data<5>.PIN; xd<13>.OE = !nxcs_i<3> & !nxoe_i & !nubs_i; xd<14> = ext_data<6>.PIN; xd<14>.OE = !nxcs_i<3> & !nxoe_i & !nubs_i; xd<15> = ext_data<7>.PIN; xd<15>.OE = !nxcs_i<3> & !nxoe_i & !nubs_i; xd<1> = nxcs_i<2> & ext_data<1>.PIN # nxoe_i & ext_data<1>.PIN # !nxcs_i<2> & !nxoe_i & user_bus<1>; xd<1>.OE = xd_0_IOBUFE/xd_0_IOBUFE_TRST; xd<2> = nxcs_i<2> & ext_data<2>.PIN # nxoe_i & ext_data<2>.PIN # !nxcs_i<2> & !nxoe_i & user_bus<2>; xd<2>.OE = xd_0_IOBUFE/xd_0_IOBUFE_TRST; xd<3> = nxcs_i<2> & ext_data<3>.PIN # nxoe_i & ext_data<3>.PIN # !nxcs_i<2> & !nxoe_i & user_bus<3>; xd<3>.OE = xd_0_IOBUFE/xd_0_IOBUFE_TRST; xd<4> = nxcs_i<2> & ext_data<4>.PIN # nxoe_i & ext_data<4>.PIN # !nxcs_i<2> & !nxoe_i & user_bus<4>; xd<4>.OE = xd_0_IOBUFE/xd_0_IOBUFE_TRST; xd<5> = nxcs_i<2> & ext_data<5>.PIN # nxoe_i & ext_data<5>.PIN # !nxcs_i<2> & !nxoe_i & user_bus<5>; xd<5>.OE = xd_0_IOBUFE/xd_0_IOBUFE_TRST; xd<6> = nxcs_i<2> & ext_data<6>.PIN # nxoe_i & ext_data<6>.PIN # !nxcs_i<2> & !nxoe_i & user_bus<6>; xd<6>.OE = xd_0_IOBUFE/xd_0_IOBUFE_TRST; xd<7> = nxcs_i<2> & ext_data<7>.PIN # nxoe_i & ext_data<7>.PIN # !nxcs_i<2> & !nxoe_i & user_bus<7>; xd<7>.OE = xd_0_IOBUFE/xd_0_IOBUFE_TRST; xd<8> = ext_data<0>.PIN; xd<8>.OE = !nxcs_i<3> & !nxoe_i & !nubs_i; xd<9> = ext_data<1>.PIN; xd<9>.OE = !nxcs_i<3> & !nxoe_i & !nubs_i; xwait_o = !nwait_i; Legend:.COMB = combinational node mapped to the same physical macrocell as the FastInput "signal" (not logically related) **************************** Device Pin Out **************************** Device : XC9572XL-7-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC9572XL-7-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 TIE 51 VCC 2 NC 52 xa_i<22> 3 TIE 53 xa_i<23> 4 en<2> 54 d_29 5 VCC 55 en<3> 6 TIE 56 irq<3> 7 NC 57 VCC 8 irq_out 58 ucs<3> 9 nxcs_i<3> 59 iord 10 nxcs_i<2> 60 ucs<2> 11 xd<7> 61 rst_out 12 xd<6> 62 GND 13 xd<5> 63 irq<2> 14 xd<4> 64 ext_data<0> 15 xd<3> 65 clk_out 16 xd<2> 66 ext_data<2> 17 xd<1> 67 ext_data<1> 18 xd<0> 68 ext_data<4> 19 NC 69 GND 20 nwait_i 70 ext_data<3> 21 GND 71 ext_data<6> 22 nxwe_i 72 ext_data<5> 23 nxoe_i 73 NC 24 NC 74 irq<0> 25 xwait_o 75 GND 26 VCC 76 ext_data<7> 27 cko_i 77 iowr 28 nbufen_io 78 ucs<1> 29 ncplden_i 79 irq<1> 30 nubs_i 80 NC 31 GND 81 ucs<0> 32 nlbs_i 82 TIE 33 xd<8> 83 TDO 34 NC 84 GND 35 xd<9> 85 TIE 36 xd<10> 86 TIE 37 xd<11> 87 en<0> 38 VCC 88 VCC 39 xd<12> 89 led<2> 40 xd<13> 90 led<3> 41 xd<14> 91 led<1> 42 xd<15> 92 led<0> 43 NC 93 TIE 44 GND 94 TIE 45 TDI 95 TIE 46 NC 96 TIE 47 TMS 97 en<1> 48 TCK 98 VCC 49 xa0_i 99 nrst_i 50 xa_i<21> 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PE = Port Enable pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-7-TQ100 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Set Unused I/O Pin Termination : FLOAT Set I/O Pin Termination : FLOAT Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25